Efabless Awards Winners of AI Silicon Design Contest (3700 × 768 px)_v2.jpg

Congratulations to the winners of the Efabless AI Generated Open-Source Silicon Design Challenge!

We would like to thank all the participants for your hard work, creativity using generative AI, and incredible speed in implementing and verifying your design through the Efabless OpenLane flow.

The winning designs are the following:


1st Place: QTCore-C1

QTCore-C1 by Hammond Pearce. The design is a co-processor that can be used for many applications, such as predictable-time I/O state machines for PIO functions as seen on some microcontrollers developed using the Chip-Chat methodology that the NYU team has published.

GitHub Repository

Learn more about the design

2nd Place: Cyberrio

Cyberrio by Xinze Wang, Guohua Yin, and Yifei Zhu at Tsinghua-Berkeley Shenzhen Institute. This design is a RISC-V CPU, implemented with Verilog code produced via a series of prompts given to ChatGPT-4.

GitHub Repository

Learn more about the Design

3rd Place: Model Predictive Control

Model Predictive Control (MPC) by Asma Mohsin and Muhammad Ali Farooq at Rapid Silicon. The design is used to predict future behavior and optimize control actions for a regulator control circuit provided in MATLAB code to ChatGPT-4 and then implemented with prompts in Verilog.

GitHub Repository

Learn more about the design


Use generative AI (e.g. chatGPT, Bard or similar) to generate a complete Verilog model for a digital design. The design must be implemented using chipIgnite that includes an SoC template (Caravel) providing rapid chip-level integration and an open-source RTL-to-GDS digital design flow (OpenLane).

A successful project must provide all prompts used to generate a complete RTL model for the design. In addition, verification testbenches that demonstrate the design meets the intended functionality must be provided and maybe created conventionally.

See the following video example.


Be among one of the first to design and tapeout an AI generated open-source silicon design. Participants will be eligible to win free fabrication for their design and receive public recognition and promotion of their design by Efabless. We are targeting to select at least three winners and designs to be fabricated based on the quality of the submissions. We are also working with industry partners to support fabricating additional projects.

In addition, each submission that meets the requirements will received a development board with a fabricated chip from one of the winning projects.

Judging Criteria:

All designs will be judged by a panel of experts who share a lifelong commitment to electronics and believe in the power of AI and machine learning to drive innovation.

  • Project Documentation
  • Prompt Documentation
  • Code
  • Verification Coverage
  • Technical Merit
  • Project Description and Community Interest Poll

Judging Panel


Evgeni Gousev

Senior Director; Qualcomm

Chairman; tinyML Foundation


J. Augusto de Oliveira

Former CTO; Cypress Semiconductor
CSO/CTO Rocky Crest Consulting
Associate Director, TD Shepherd


Naveed Sherwani

Chairman, President & CEO; RapidSilicon


Brandon Wang

Head of Chief Innovation Office and VP, Corporate Strategy and New Ventures; Synopsys


Weijie Yun

Founder and Managing Partner; Tyche Partners