Congratulations to Xinze Wang, Guohua Yin, and Yifei Zhu at Tsinghua-Berkeley Shenzhen Institute for winning the second-place prize in the Efabless AI Generated Design Contest!

Welcome to the Q&A with Cyberrio by Xinze Wang, Guohua Yin, and Yifei Zhu. The team will be discussing the RISC-V CPU design, implemented with Verilog code produced via a series of prompts given to ChatGPT-4.

What was your goal and/or why did you choose this design?

I hope to be able to complete a CPU by using GPT-4 and as few prompts as possible. There are a lot of handshake information and parallel logic in the CPU.

How did you implement your project? What challenges did you run into and what did you learn?

Initially, I set up a robust validation environment, then individually generated and validated each module using GPT-4. If issues arose, I attempted to rectify them with GPT-4, starting with simple prompts and gradually introducing more complex ones until the validation environment ran smoothly. However, GPT-4's capabilities in hardware programming significantly trail behind those in software. For concurrency and handshakes, you must provide exhaustive instructions; otherwise, it won't complete the task. Besides, the output often comes with syntax and logic issues, requiring manual inspection. GPT-4 doesn't have a firm grasp on certain detailed knowledge either, which might call for the integration of Langchain to build a knowledge base for operation.

How would you extend your project or what would you do next time?

I think that on the one hand, I may choose open source GPT models such as Llama or Bloom to try. At the same time, I will try to train these models to enhance the ability of hardware languages. On the other hand, I will try to combine Langchain to build a knowledge base and build an API on the server side. Automatically capture operational feedback, making it easier for humans to generate a design.