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Join the First Efabless Chipalooza Analog and Mixed-Signal Design Challenge

About the Challenge

The next generation of Caravel harness chip will be a major enhancement of the existing Caravel chip, targeting IoT machine learning applications by giving the designer many more resources to choose from than a processor. IoT applications connect to the real world, so they need analog-to-digital and digital-to-analog conversion, signal conditioning (amplifiers, biasing, and filtering), analog signal processing, power management (to maintain ultra-low power consumption for battery-operated applications), temperature sensing, and more.

In this design challenge, we invite designers to create open-source chip-based IP for IoT machine learning applications from a list we’ll provide.

Why it Matters

The benefits of new analog and mixed-signal circuits will be multi-fold. Competitive designs will be made available on the next-generation Caravel architecture as resources for designers needing input from and output to the real world, signal conditioning, power management, and analog signal processing. At the same time, all designs will become part of the first major open-source collection of analog and mixed-signal IP in the world, available for re-use and enhancement for academic, commercial, and personal applications.

Awards to Submitters

Designers or teams whose design proposals are approved for further development will receive a free TinyTapeout entry, valued at $300, and a T-shirt. Note that future Tiny Tapeouts will include analog design slots.

Those who successfully complete the schematic and simulation phase and pass the design review will earn an additional TinyTapeout entry. Teams fulfilling all required deliverables, adhering to guidelines, meeting circuit specifications, and passing the final post-layout design review will be awarded a free quarter slot on a future ChipIgnite shuttle run. This allows them to implement any design of their choice, whether analog or digital, valued at approximately $2,500.

Furthermore, each team will be provided with a development board and a packaged test chip from the April shuttle run featuring their design. While teams are expected to perform basic functional verification of their block using the test chip, full characterization is not required.

Finally, completed designs will be selected for inclusion in the official next-generation Caravel harness.

The Rules

  1. To view a list of IP blocks available for the next-generation Caravel, please click here. For each IP block, Efabless will provide the following:
    1. Specification including performance metrics to be met
    2. Pinout for the block
    3. Maximum area in which the design must fit
  2. Designers will write up and submit a simple proposal declaring which IP block they propose to design, and what architecture they plan to use to meet the specification.
  3. Proposals will be reviewed and accepted based on need and design team capability.
  4. Designers are encouraged to submit multiple proposals, as all blocks on the list need to be designed to make a competitive future Caravel harness.
  5. For the assessment of design team capability: Designers must show in the proposal that they have a good understanding of analog circuit design and are familiar with the principles and limitations of the circuit architecture they have adopted for their design.
  6. Designers will have a specific set of deliverables for each design review, including the proposal, then schematic and simulations, then layout and verification.
  7. Specifications provided by Efabless are not necessarily final, and any design group may request a review of a specification if they believe that the specification is impossible to meet, or meeting a circuit specification will degrade the circuit performance in other ways. All specification changes must be approved by Efabless.
  8. All designs will be submitted in the form of an open-source git repository and must contain all required design files, the original specification, and a datasheet with results and plots. The file structure of the repository will follow standard guidelines.
  9. No proprietery tools may be used in the design process.
  10. The final deliverable will be a GDS file of the circuit block layout. Designers will not integrate the block into a Caravel user project, but integration of multiple projects into one or more chipIgnite slots will be done by Efabless, with project grouping at the discretion of Efabless.
  11. The target tapeout date for integrated projects is the April 24 chipIgnite shuttle run closing date.

Deadlines

Dates Activity
16-February Launch Challenge
01-March Submit Proposals
05-March Proposals Reviewed/Accepted
07-March Schematic/Simulation Workshop
22-March Schematics Due
25-March Schematic Design Review
27-March Layout/Extraction Workshop
01-April Physical Verification Workshop
15-April Layout Due
17-April Post-Layout Design Review
24-April Shuttle Run Close Date

Resources

Efabless will provide a standard circuit review process, including proposal review, schematic review, layout review, and final sign-off. Throughout the period between the Chipalooza launch and the close of the shuttle run, there will be webinars on how to use the available open source schematic and layout tools and principles of good analog and mixed-signal design, along with workshops for helping designers get through the process and make it to tapeout with a competitive project which meets industry standards for best practices

Webinar Recording and Slides

For an overview of the design challenge and its goals, access the slides from our February 16 webinar here.

For the webinar recording, click here.

*Free slots are subject to availability; please reserve a space well in advance of a shuttle run closing date.