Join the 2nd

AI Generated Open-Source Silicon
Design Challenge

Witness firsthand how Generative AI is transforming the chip design landscape, empowering you to easily create cutting-edge designs with unlimited potential in less than two months!

Description

Use generative AI (e.g. chatGPT, Bard or similar) to generate a complete Verilog model for a digital design. The design must be implemented using chipIgnite that includes an SoC template (Caravel) providing rapid chip-level integration and an open-source RTL-to-GDS digital design flow (OpenLane).

A successful project must provide all prompts used to generate a complete RTL model for the design. In addition, verification testbenches that demonstrate the design meets the intended functionality must be provided and maybe created conventionally.

See the following video example.

Also checkout the winners from the first contest.

Award:

Be among one of the first to design and tapeout an AI generated open-source silicon design. Participants will be eligible to win free fabrication for their design and receive public recognition and promotion of their design by Efabless. We are targeting to select at least three winners and designs to be fabricated based on the quality of the submissions. We are also working with industry partners to support fabricating additional projects.

In addition, each submission that meets the requirements will received a development board with a fabricated chip from one of the winning projects.

How to Enter

1. Register on the Efabless platform if you have not already done so.
2. Join the challenge channel #generative-ai-silicon-challenge on open-source-silicon.dev Slack space for updates and additional help and resources.
3. Submit your entry by including all content on a public GitHub repo.
4. Create a public project for the chipIgnite CI 2309 shuttle using the GitHub repo from the previous step. Please include AI-design-contest in the label field when you create your project.
5. Submit success precheck and tapeout jobs for your design.
6. Complete the remainder of the billing and shipping information as well as terms and export agreements. You will not be charged or invoiced for your submission. Complete the final submission for the project on the platform.
7. Send an email to shuttle@efabless.com with a link to your project.

Limit one entry per person, per email address. Your entry must be original.

Note: If you have not received permission to use copyrighted material, you may not include the material in your entry.

Judging Criteria:

All designs will be judged by a panel of experts who share a lifelong commitment to electronics and believe in the power of AI and machine learning to drive innovation. Stay tuned for more details!

• Project Documentation
• Prompt Documentation
• Code
• Verification Coverage
• Technical Merit
• Project Description and Community Interest Poll

All requirements must be met to be eligible to win

1. All submission content, documentation, prompt must be in English
2. A short description of the project must be included with your design. It will be used for introducing your idea in the community poll.
3. All designs must be implemented and fit in the Caravel User Project area.
4. The Verilog for the design must be coded by AI.
5. Verification may be done outside of the AI environment but verification testbenches must be provided as a reproducible element of this process.
6. All prompts or auto GPT session logs used in the design must be provided as part of the deliverables for the design.
7. The design needs to be open source with all materials required to reproduce made public.
8. To facilitate reproducibility by the community, we recommend the design be implemented using the OpenLane chipIgnite flow including all configuration and run results. However, we will accept any open-source implementation flow provided it is documented and reproducible.
9. Must have testbenches for RTL verification as well as constraints for STA and SDF simulations.
10. Must be implementable in SKY130 with available standard cells and DFFRAM and not require open RAM or other discrete memories for implementation.
11. The design must pass precheck and tapeout submissions on the Efabless platform.
12. Winners must provide a video and screenshots demonstrating the creation of the project in a how-to or step-by-step format. The images and link to the video must be included in the documentation for their project in the GitHub repo. These materials may be used by Efabless for promotional purposes.

Official Rules

Eligibility

Participants must be able to receive silicon and parts shipped from the United States. As such, members of United States embargoed or sanctioned countries are not eligible to participate.

Current employees of Efabless or their family members are also not eligible to participate.

Deadline

The submission deadline has been extended to Thursday, September 7, 2023 at 11:59 pm PT.

Sponsorship

The contest is sponsored by Efabless Corporation, 165 University Ave, Palo Alto, CA 94301

Agreement to Official Rules

Participation in the contest constitutes participant’s full and unconditional agreement to and acceptance of these Official Rules and the decision of the Sponsor, which are final and binding.

An entry may be rejected at the sole and absolute discretion of Efabless.

By entering the contest, you agree and allow Efabless to use, display, and publish a winner's identity, including their name and photo, in promotional materials. The participants also agree that Efabless has the right to use participant’s designs and other material in sales and marketing.

Contest Winner Announcement

Contest winners will be announced on Thursday, September 14, 2023.

The winner will be provided fabrication at no cost in the September 11th, chipIgnite shuttle, CI 2309.

Contact

Please contact shuttle@efabless.com if you have any questions about this contest.

We also created a channel on our community Slack site. Please feel free to reach out to us there and follow updates on the contest.

Privacy Policy

See our privacy policy for more information.