We would like to thank all the participants for your hard work, creativity using generative AI, and incredible speed in implementing and verifying your design through the Efabless OpenLane flow.

The winning designs are the following:

Description

Use generative AI (e.g. chatGPT, Bard or similar) to generate a complete Verilog model for a digital design. The design must be implemented using chipIgnite that includes an SoC template (Caravel) providing rapid chip-level integration and an open-source RTL-to-GDS digital design flow (OpenLane).

A successful project must provide all prompts used to generate a complete RTL model for the design. In addition, verification testbenches that demonstrate the design meets the intended functionality must be provided and maybe created conventionally.

See the following video example.

Award:

Be among one of the first to design and tapeout an AI generated open-source silicon design. Participants will be eligible to win free fabrication for their design and receive public recognition and promotion of their design by Efabless. We are targeting to select at least three winners and designs to be fabricated based on the quality of the submissions. We are also working with industry partners to support fabricating additional projects.

In addition, each submission that meets the requirements will received a development board with a fabricated chip from one of the winning projects.

Judging Criteria:

All designs will be judged by a panel of experts who share a lifelong commitment to electronics and believe in the power of AI and machine learning to drive innovation.

• Project Documentation
• Prompt Documentation
• Code
• Verification Coverage
• Technical Merit
• Project Description and Community Interest Poll