Use generative AI (e.g. chatGPT, Bard or similar) to generate a complete Verilog model for a digital design. The design must be implemented using chipIgnite that includes an SoC template (Caravel) providing rapid chip-level integration and an open-source RTL-to-GDS digital design flow (OpenLane).
A successful project must provide all prompts used to generate a complete RTL model for the design. In addition, verification testbenches that demonstrate the design meets the intended functionality must be provided and maybe created conventionally.
See the following video example.
Be among one of the first to design and tapeout an AI generated open-source silicon design. Participants will be eligible to win free fabrication for their design and receive public recognition and promotion of their design by Efabless. We are targeting to select at least three winners and designs to be fabricated based on the quality of the submissions. We are also working with industry partners to support fabricating additional projects.
In addition, each submission that meets the requirements will received a development board with a fabricated chip from one of the winning projects.
Limit one entry per person, per email address. Your entry must be original.
Note: If you have not received permission to use copyrighted material, you may not include the material in your entry.
All designs will be judged by a panel of experts who share a lifelong commitment to electronics and believe in the power of AI and machine learning to drive innovation. Stay tuned for more details!
Senior Director; Qualcomm
Chairman; tinyML Foundation
J. Augusto de Oliveira
Former CTO; Cypress Semiconductor
CSO/CTO Rocky Crest Consulting
Associate Director, TD Shepherd
Chairman, President & CEO; RapidSilicon
Head of Chief Innovation Office and VP, Corporate Strategy and New Ventures; Synopsys
Founder and Managing Partner; Tyche Partners
Participants must be able to receive silicon and parts shipped from the United States. As such, members of United States embargoed or sanctioned countries are not eligible to participate.
Current employees of Efabless or their family members are also not eligible to participate.
The submission deadline has been extended to Saturday, June 3, 2023 at 11:59 pm PT.
The contest is sponsored by Efabless Corporation, 165 University Ave, Palo Alto, CA 94301
Participation in the contest constitutes participant’s full and unconditional agreement to and acceptance of these Official Rules and the decision of the Sponsor, which are final and binding.
An entry may be rejected at the sole and absolute discretion of Efabless.
By entering the contest, you agree and allow Efabless to use, display, and publish a winner's identity, including their name and photo, in promotional materials. The participants also agree that Efabless has the right to use participant’s designs and other material in sales and marketing.
Contest winners will be announced on Friday, June 9 2023.
The winner will be provided fabrication at no cost in the June 5th chipIgnite shuttle, 2306Q.
Please contact email@example.com if you have any questions about this contest.
We also created a channel on our community Slack site. Please feel free to reach out to us there and follow updates on the contest.
Most but not all. We are open to interpretation to enable the challenge to move ahead.
You may but that would likely not be very interesting.
The question is vague, Which specific IP are you referring to? Any IP used must be open sourced.
Either manually or through AI is interesting. We are most interested in novel IP development.
Up to the participants.