Make Your Own Chips for Free

Design and fabricate your own open-source design for free with the Open MPW Program

MPW-7 Submission Deadline is September 12

Welcome to the Efabless Open MPW Program


The shuttle provides opportunities for designers to experiment and push the state-of-the-art without having to reconcile the risk associated with the cost of fabrication.
The shuttle program is open to anyone, provided that their project is fully open source and meets the other program requirements.
Costs for fabrication, packaging, evaluation boards and shipping are covered by Google for this program.

Open-source PDK

Open-source EDA Tools

Free Fabrication

Eight shuttles, 40 slots per shuttle, free to designers of fully open-source IC and IP designs.
SkyWater open-source 130nm PDK

Open Source Design Flow - OpenLane “Compiler”

OpenLane is a no-human in the loop RTL to GDS compiler built around OpenROAD that works like a GNU software compiler with trade-offs in area and performance.
It opens the door for every software developer to generate hardware representation without the need for details. That’s at least a 1000x more potential designers!


Caravel - Full Chip Open-source Design

Integrated you project into full chip providing power, configurable IOs and a RISC-V management SoC.


Project Submission Requirements

The following project requirements must be met in order to qualify for inclusion on the shuttle program:

  • The project must be targeted on the currently-supported SkyWater Open PDK for the 130nm process.
  • The project must be posted on a git-compatible repo and be publicly accessible.
  • The top-level of the project must include a LICENSE file for an approved open-source license agreement. Third-party source code must be identified and source code must contain proper headers. See details here.
  • The repo must include project documentation and adhere to Google's inclusive language guidelines. See details here.
  • The project must be fully open. The project must contain a GDSII layout, which must be reproducible from source contained in the project.
  • Projects must use a common test harness and padframe based on the Caravel repo. New projects should start by duplicating or forking the Caravel User Project repo and implementing their project using the user_project_wrapper. The Caravel repo is configured as a submodule in the project under the ‘caravel’ directory. Note -- you do not need to initialize nor clone the Caravel sub-directory to complete or submit your project. See the project README for further instructions. The projects must be implemented within the user space of the layout and meet all requirements for the Caravel.
  • Projects must successfully pass the Open MPW precheck tool, including LVS and DRC clean using the referenced versions of OpenLane flow. Projects should implement and pass a simulation test bench for their design integrated into Caravel. The Caravel User Project provides an example of how to implement this.


  • April 11, 2022: Project submission is OPEN
  • June 8, 2022: Project submission is CLOSED
  • August 30, 2022: Wafer fabrication complete, packaging and assembly begins
  • October 18, 2022: Parts and assembled boards shipped to project owners


In order to submit a project for the Open MPW program, complete the following steps:

  1. Create a project using a public git repo from the My Projects page
  2. Execute precheck verification tool on your project’s workspace, fix any problems on your repo and re-run precheck
  3. Download this form and complete and submit via the request
  4. Review and complete your MPW service agreement
  5. Review deliverables of your MPW request and select ‘Submitter Confirmed’ when complete.
    The request is found on the "Requests" tab of your project.

Note: To withdraw your submission, go to the 'requests' tab on your MPW-5 project page, and close your request.

Previous Shuttle Projects



45 designs submitted in 30 days!

9 x Open processor cores

9 x SoC’s

Crypto-currency Miner

Robotic App Processor

Amateur Satellite Radio Transceiver

7 x Analog/RF

5 eFPGA’s


56 designs submitted in 30 days!

11 x Open processor cores

11 x SoC’s


Time to Digital Converter - LIDAR

Multi-project harness for Caravel

17 x Analog/RF

3 eFPGA’s