MEDIA ALERT: Efabless to Present RISC-V Workshop Talk on Creating Mixed-Signal ASIC Using Open Source Implementation Toolset

Will Describe Designing, Verifying, Implementing RISC-V Mixed-Signal ASIC with Open Source RTL-to-GDS Toolset

SAN JOSE, CA–(Marketwired – Nov 20, 2017) –

WHO: Efabless corporation, an online hardware design marketplace for community-developed hardware, including semiconductor intellectual property (IP) and customized integrated circuits (ICs)

WHAT: Will present “PicoSoC: How we created a RISC-V based ASIC processor using a full open source foundry-targeted RTL-to-GDS flow, and how you can, too!” during the RISC-V Workshop

WHEN: Wednesday, November 29

WHERE: Western Digital Corporate Campus, 951 Sandisk Drive, Building 2, Milpitas, Calif.

The presentation will be given by Tim Edwards, efabless’ senior vice president of analog platform engineering, who will describe designing, verifying and implementing a RISC-V based mixed-signal ASIC using open source RTL-to-GDS implementation toolset. The ASIC utilizes the open-source RISC-V IP core designed for deep embedded applications implemented in 180nm foundry technology using the efabless’ design framework.

About Efabless is the world’s first semiconductor community engineering platform, connecting a global community of mixed signal architects, designers and engineers with IC, foundry and OEM customers. It provides community members with everything required to define, develop and monetize their IP and IC designs. efabless applies the principles of open innovation to make customized, on-demand mixed signal electronics affordable, accessible and creative. The efabless community spans approximately 1,400 members from more than 50 countries around the world.

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Twitter: @efabless