With the challenge underway, a few of the participants have identified a few errors and inconsistencies in the challenge spec sheet and characterization, which this update corrects. The changes included in this update are described below. We want to thank all of the
participants who have identified issues and brought them to our attention.
The update procedure is manual, and instructions for updating are provided below. The update is voluntary only in the sense that we are not automatically changing contents of any user’s design workspace. However, be aware that upon submission, the final project characterization will use the updated spec sheet and testbenches. To ensure that your submission will pass all tests, you should perform this update. By following the instructions below, none of your existing schematics or simulations will be affected. This update only changes files used by the characterization tool.
Challenge issues resolved by this update:
- The testbenches used by the automatic characterization for temperature and voltage coefficients used SPICE functions that can have incorrect results at the endpoints, leading to incorrect minimum and/or maximum values in the characterization result. These testbenches have been corrected.
- Trim values specified by X-Fab were incorrectly reversed in the original spec sheet. As a 2s-complement value, the trim value maximum 0111 (+7) corresponds to the lowest output voltage, and the trim value minimum 1000 (-8) corresponds to the highest output voltage. This may require reversing the trim wiring if schematics have been designed to the reversed specification.
- The temperature limit for the temperature coefficient measurement has been changed from 125 to 124.99 to avoid a bug in ngspice which has been reported to the ngspice developers and is currently under investigation.
- The specification for the PSRR negative measurement has been relaxed from -60dB to -10dB. The lack of a deep nwell in this process means that the substrate and ground rail cannot be isolated, and there is no way to meet the original spec. The PSRR negative measurement now mainly checks that the VBBA pin connects to substrate.
- Additional electrical parameter tests have been added to make sure that all trim bits are properly exercised. Linearity of the trim setting was implied in the original specification but not explicitly tested.
- The 1pF load capacitance listed in the global conditions of the spec sheet has been moved from the “maximum” column to “typical”. This change does not affect characterization.
How the update may affect your existing design:
Only change (2) above is likely to affect an existing design. If your circuit already implements the output voltage trimming, then the trim wiring will need to be modified to make the output voltage lowest at setting TR_BG[3:0] = 0111, and highest at setting TR_BG[3:0] = 1000.
How to obtain the update:
Go to the Efabless website, proceed to “X-Fab Challenge”, and re-accept the challenge exactly as you did the first time.
How to install the update:
- Once the challenge has been re-accepted, a new entry will appear in the “Imports” section of the project manager on Open Galaxy.
- Select the new entry in “Imports”
- Click on “Import As”. A pop-up window will appear, telling you that a project of that name already exists, and that you should choose a new name.
- Replace the name “XBG_1V23LC_V01” with the name “update”, then click “okay”.
- Right-mouse-click on the desktop background and select “Open Terminal Here”.
- Type the following commands in the terminal:
- cd ~/design
- cp update/update.json XBG_1V23LC_V01/XBG_1V23LC_V01.json
- cp update/testbench/* XBG_1V23LC_V01/testbench
- Close the characterization tool if it is open, and restart it.