Hello Efabless community
On July 13 2017 we released an open source framework, called Chiplicity, that provides designers with everything needed to design, verify, validate and prototype mixed signal ASIC products. This is a first of its kind and our objective is to simplify the path from an idea to a real testable silicon, and make this capability available to our global community of designers.
We begin the Chiplicity initiative with an open source mixed signal chip called Hydra and the IP and tools required for you to modify it and build your own ICs – from idea to GDS. We provide a set of library components in the marketplace – the Hydra open source chip, analog IP, a standardized pad frame and a serial interface (SPI). The community member can “clone” these into their own work space on the Efabless MyLib repository. The final designs can then be promoted to the marketplace for sharing with others.
We will soon provide an open source test board for the Hydra as part of the library components in the marketplace to validate custom analog circuit designs. Community members also have the option to manufacture their design through Efabless on shuttles with X-FAB.
As part of our digital library, we include a “soft” RISC-V core called PicoRV32 developed by Clifford Wolf. Over time, we will provide additional microprocessor cores, as well as additional custom analog and digital IP. We will include other open source IP and new community developed analog blocks. You will be able to share your designs under proprietary or open source licenses. Today we support the X-FAB 350nm node. We will be adding other process technologies with 180nm next on our list.
We view Chiplicity as a big step on our mission to advance open innovation in ICs and we view open innovation to be critical if ICs are to keep pace with the overall revolution in smart hardware design. Please login at efabless.com, and try it out – for commercial, “maker” or academic purposes. Most of all, please let us know your thoughts.
The Efabless team