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2018 Year in Review

Published by Team Efabless on

Dear Friends of efabless

First of all, Happy New Year to all of you and many thanks for your continuing support of efabless throughout 2018. Last year, we focused on expanding our ecosystem, our marketplace offering and taking the first steps in demonstrating and exercising the commercial model. Here are some of the highlights of the past year.

  • Strategic Partnerships: We proudly announced our partnerships with:
  1. Chipus Microelectronics, a semiconductor company with proven expertise in the development of ultra-low-power, low-voltage, analog and mixed-signal ICs and systems on chip (SoCs).
  2. Sankalp Semiconductor, an end-to-end design services provider offering an integrated portfolio of services and solutions to its customers in key semiconductor domains including digital, analog, high-speed physical interface IP, embedded memory compilers and EDA modelling.
  3. Symmid Corporation, the largest fab-independent Malaysian design group with world-class expertise in analog, digital, mixed-signal and high-voltage IC design.
  • Customer Offering: We announced two key Efabless offerings
  1. Design Request – A streamlined process to enable OEM’s and ODM’s to access design partners and community professionals.
  2. Design Your ASIC – An all-in-one offering to enable ASIC developers to start their design in minutes with access to IP, design tools and MPW shuttles.
  • New Customer Engagements: Our customers are using efabless’ online design platform to design their ASIC’s. Two designs are now underway. One customer has MPW samples expected in February.
  • Arm TechCon2018: We collaborated with Arm to present and demonstrate our SoC design platform at TechCon2018. The presentation, titled “Enabling ASICs for IoT”, features a Cortex M0-based SoC design, called Raptor, using X-FAB’s 180nm technology. Raptor is coming soon to efabless’ marketplace and will be available to SoC designers to clone and customize in minutes.
  • Open Source Chips: We released Raven, a RISC-V-based SoC that is fully designed and implemented using an open source design tool set available on efabless’ platform. The design is built using the PicoRV32 RISC-V core designed by Clifford Wolf and X-FAB’s 180nm mixed-signal IP. Raven has been taped out last August and will be back from the fab this month. An open source version of Raven is available now on GitHub.

We thank you again for your support and encourage you to use efabless to design new IP as well as reuse the available SoC reference designs with no upfront cost. You can also use the platform to request IPs, ASICs or other design services.

Happy New Year to everyone and best wishes for a wonderful 2019.

Regards

The Efabless Team