We are excited to announce the winners of the 2nd AI Generated Design Contest!
The top three winning designs will be fabricated by Efabless and delivered to their respective design teams in the form of packaged parts and evaluation boards.
Other entrants with qualifying designs will receive a free evaluation board and one of the winning AI-designed chips.
AI by AI by Emilio Isaac Baungarten Leon. The design is a dedicated hardware Integrated Circuit (IC) for a Convolutional Neural Network (CNN) that classifies the MNIST dataset written with the help of ChatGPT and documents the entire design process from the Python environment of TensorFlow to Verilog. This approach demonstrates the incredible possibilities of AI-driven design.
MASC-AI-Synthesized-Cryptoprocessor by Mark Zakharov. This design is a RISC-V Crypto extension leveraging the capabilities of GPT-4. The unique aspect of this project is the use of DSLX as the hardware description language, verification with co-simulation code generated by GPT-4, and additional automatically generated verification tests.
Caravel-Vector-Coprocessor-AI by William Salcedo. The design adds basic vector instructions to the Caravel Management SoC. All code, besides file paths, was written using ChatGPT. This includes test cases, C libraries, blocks, etc. In this project, GPT-4 served as a pair programmer which followed the instructions of a human that was aware of how the microarchitecture would look.
The winners of the 2nd Efabless AI Generated Open-Source Silicon Design Challenge have shown what is possible when generative AI is used to design chips.
Congratulations to our winners and thank you to all participants for being a part of this incredible AI-driven design challenge!
Use generative AI (e.g. chatGPT, Bard or similar) to generate a complete Verilog model for a digital design. The design must be implemented using chipIgnite that includes an SoC template (Caravel) providing rapid chip-level integration and an open-source RTL-to-GDS digital design flow (OpenLane).
A successful project must provide all prompts used to generate a complete RTL model for the design. In addition, verification testbenches that demonstrate the design meets the intended functionality must be provided and maybe created conventionally.
See the following video example.
Be among one of the first to design and tapeout an AI generated open-source silicon design. Participants will be eligible to win free fabrication for their design and receive public recognition and promotion of their design by Efabless. We are targeting to select at least three winners and designs to be fabricated based on the quality of the submissions. We are also working with industry partners to support fabricating additional projects.
In addition, each submission that meets the requirements will received a development board with a fabricated chip from one of the winning projects.
All designs will be judged by a panel of experts who share a lifelong commitment to electronics and believe in the power of AI and machine learning to drive innovation.
Senior Director; Qualcomm
Chairman; tinyML Foundation
J. Augusto de Oliveira
Former CTO; Cypress Semiconductor
CSO/CTO Rocky Crest Consulting
Associate Director, TD Shepherd
Chairman, President & CEO; RapidSilicon
Head of Chief Innovation Office and VP, Corporate Strategy and New Ventures; Synopsys
Founder and Managing Partner; Tyche Partners
Dr. Hammond Pearce
Lecturer (Assistant Professor) at UNSW Sydney School of Computer Science and Engineering