Thank you for being part of this groundbreaking journey. You've redefined what's possible at the intersection of AI and chip design.
We are excited to announce the winners of the 3rd AI Generated Design Contest!
The top three winning designs will be fabricated by Efabless and delivered to their respective design teams in the form of packaged parts and evaluation boards.
The project is contributed by EDABK Lab, School of Electronics and Electrical Engineering, Hanoi University of Science and Technology (HUST).
This project ambitiously aims to develop a hardware-software co-designed neurosynaptic core leveraging Spike Neural Network (SNN) architecture. This core will be seamlessly integrated into a RISC-V based SoC, powered by advanced optimizations applied to RTL code generated by ChatGPT-4.
This AI-powered 3-phase PWM circuit, generated using ChatGPT-4, offers precise and safe control of power electronics. It generates six PWM waveforms with adjustable duty cycles, each 120 degrees out of phase, ensuring smooth and efficient operation. Additionally, dead time is incorporated to prevent short circuits, making it ideal for demanding applications.
This project uses Amaranth, a Python HDL, to generate a hardware PRNG design, leveraging Microsoft Bing Chat for information and guidance. It includes simulation, Dieharder testing, and Verilog output for Caravel integration. A detailed write-up is available on arxiv.org.
Key Takeaways:
Congratulations to our winners and thank you to all participants for being a part of this incredible AI-driven design challenge. Your participation and collaboration were invaluable.
Use generative AI (e.g. chatGPT, Bard or similar) to generate a complete Verilog model for a digital design. The design must be implemented using chipIgnite that includes an SoC template (Caravel) providing rapid chip-level integration and an open-source RTL-to-GDS digital design flow (OpenLane).
A successful project must provide all prompts used to generate a complete RTL model for the design. In addition, verification testbenches that demonstrate the design meets the intended functionality must be provided and maybe created conventionally.
See the following video example.
Be among one of the first to design and tapeout an AI generated open-source silicon design. Participants will be eligible to win free fabrication for their design and receive public recognition and promotion of their design by Efabless. We are targeting to select at least three winners and designs to be fabricated based on the quality of the submissions. We are also working with industry partners to support fabricating additional projects.
In addition, each submission that meets the requirements will received a development board with a fabricated chip from one of the winning projects.
All designs will be judged by a panel of experts who share a lifelong commitment to electronics and believe in the power of AI and machine learning to drive innovation.
Evgeni Gousev
Senior Director; Qualcomm
Chairman; tinyML Foundation
J. Augusto de Oliveira
Former CTO; Cypress Semiconductor
CSO/CTO Rocky Crest Consulting
Associate Director, TD Shepherd
Naveed Sherwani
Chairman, President & CEO; RapidSilicon
Brandon Wang
Head of Chief Innovation Office and VP, Corporate Strategy and New Ventures; Synopsys
Weijie Yun
Founder and Managing Partner; Tyche Partners
Dr. Hammond Pearce
Lecturer (Assistant Professor) at UNSW Sydney School of Computer Science and Engineering
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