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Webinar: How to design a RISC-V SoC

“Making the Raven chip: How to design a RISC-V SoC”

Brought to you by efabless and VLSI System Design

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Introducing X-FAB’s XH018 (180nm) Process to efabless’ Chiplicity Platform

As promised at the end of last year, in January we introduced the first variant of 180nm process technologies to our Chiplicity framework, the XH018 from X-FAB and all the supporting analog/mixed-signal IP blocks from X-FAB. .. read more

2017 Year in Review

It has been an exciting year for efabless and our community members. In 2017 we have made significant strides toward our vision… read more

re.DEFINING

Hardware Product Creation

We simplify the process of Smart Product creation and open it to everyone

Final Challenge Series Results Posted !!

See the Challenge Series Results

GO CONFIGURE DESIGN CHALLENGE SERIES

We’ve just completed the Go Configure Design Challenge Series featuring GreenPAK, a configurable mixed-signal technology from Dialog.  Check out the link below to learn more.