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Overcoming SPICE Convergence Issues

Published by Team Efabless on

In this article, we will be address techniques for resolving simulation convergence issues. Simulation convergence issues arise from a variety of reasons that prevent the simulator from reaching a valid solution within a certain number of iterations. In general convergence issues can be grouped in the following high-level buckets:

  • Circuit topology errors or bad practices
  • Simulator control or options
  • Modeling abnormalities

As a general rule, there is not a single set of issues or golden solutions that apply to all circuits devices or conditions. It is very important that the designer understands the capabilities and limitations of simulation models as well as the approaches used by the simulators to arrive to a valid solution.

Usually the designer does not have the ability to modify device models unless they are developed by the designer – like in the case of behavioral models or macro-models constructed from primitive SPICE components. Included below are some of the key guidelines and simulator settings that could be applied to the specific simulation setup.

Possible circuit topology errors or bad design practices

  • Nodes with one connection
  • No DC current path to ground
  • Circuits with multiple valid operating point solutions
  • Excessively large values of components and/or voltage/current sources
  • Unrealistically fast rise/fall sources
  • Unrealistic initial conditions

Simulator control or options

The simulator settings, error tolerances and algorithms & methods used to solve the matrix do not apply to all circuits or simulation experiments being run. The options are used with the .OPTION statement for ngspice. For more information about these options, please refer to the ngspice User Manual.

DC Solution Options

  • ABSTOL=x resets the absolute current error tolerance of the program. The default value is 1 pA.
  • GMIN=x resets the value of GMIN, the minimum conductance allowed by the program. The default value is 1.0e-12.
  • RELTOL=x resets the relative error tolerance of the program. The default value is 0.001 (0.1%).
  • RSHUNT=x introduces a resistor from each analog node to the ground. The value of the resistor should be high enough to not interfere with circuit operations.
  • ITL1=x resets the dc iteration limit. The default is 100.
  • VNTOL=x resets the absolute voltage error tolerance of the program. The default value is 1 μV.

Transient Options

  • GMINSTEPS=x sets number of Gmin steps to be attempted. If the value is set to zero, the gmin stepping algorithm is disabled. In such case the source stepping algorithm becomes the standard when the standard procedure fails to converge to a solution.
  • ITL3=x resets the lower transient analysis iteration limit. the default value is 4.
  • ITL4=x resets the transient analysis time-point iteration limit. the default is 10.
  • ITL5=x resets the transient analysis total iteration limit. the default is 5000.

Use of Initial Conditions

  • .NODESET Specify Initial Node Voltage Guesses. The .nodeset line helps the program find the dc or initial transient solution by making a preliminary pass with the specified nodes held to the given voltages. The restriction is then released and the iteration continues to the true solution. The .nodeset line may be necessary for convergence on bistable or a-stable circuits.
  • .IC Set Initial Conditions. The .ic line is for setting transient initial conditions. It has two different interpretations, depending on whether the uic parameter is specified on the .tran control line. Also, one should not confuse this line with the .nodeset line. The .nodeset line is only to help dc convergence, and does not affect final bias solution (except for multi-stable circuits).

Suggested Options & Settings

Included below are some of the settings we have used and applied to address the convergence issues for DC and Transient simulations. The suggested values below are not intended as a blanket one-fix-for-all values. If you are still facing convergence failures, it is advised that the designer would consult the ngspice users manual or contact the Efabless Helpdesk.

  • .OPTION ABSTOL=1e-15.
  • .OPTION GMIN=1.0e-12.
  • .OPTION ITL1=1e5
  • .OPTION RSHUNT=1e12
  • .OPTION RELTOL=1e-5

References and publicly available articles

To get more information about the SPICE simulation convergence failure please see links below:

  1. NGSPICE User’s Manual
  2. Step-by-step procedures help you solve Spice convergence problems
  3. Achieving Accurate Results with a Circuit Simulator
  4. Practical Methods for Verifying Removal of Trojan Stable Operating Points
  5. A Study on Components Sizing for CMOS Bandgap Voltage References