SoC Configurator (raptor)

    Core & Memory Configuration
    CPU Description
    Hardened ARM Cortex M0 microprocessor for embedded applications.
    Static RAM Description
    X-Fab 12-bit address x 32 bit data single-port SRAM

    Clocking System
    Source Clock Description
    External 1 – 4 MHz crystal oscillator. 
    Type Minimum | Maximum Value
    System Maximum 16.0 Mhz
    Peripheral Maximum 16.0 Mhz
    Internal 1 MHz RC oscillator with internal R and C.
    Type Minimum | Maximum Value
    System Maximum 8.0 Mhz
    Peripheral Maximum 8.0 Mhz

    ARMAHBL Peripherals

      Slot Peripheral Description Stop Mode IRQ
      1 AHB compatible QSPI peripheral to communicate with external SPI Flash Memory. It is designed... FIXED
      Option Value
      Boot Mode
      Up to 10 more AHB peripherals can be added

      ARMAPB Peripherals

            Slot Peripheral Description Stop Mode IRQ
            1 UART interface controller for APB bus. FIXED
            2 UART interface controller for APB bus. FIXED
            3 SPI master controller for APB bus. FIXED
            Up to 13 more APB peripherals can be added

            Components I/O

            None None None
            Component Core Area (mm²) Required Pins Optional Pins Pin Total
            Arm Cortex M0 - v3.0 0.68671
            High Speed SRAM (16kB) - v1.0 0.84888
            AHB QSPI Flash Interface - v1.0 0.00984
            UART (APB) - v1.0 0.05256
            UART (APB) - v1.0 0.05256
            SPI Master (APB) - v1.0 0.00984
            Raptor Power Circuit - v1.0 0.00244
            Raptor JTAG Controller - v1.0 0.00782
            AHB ROM - v1.0 0.00036
            AHB Debug IO - v1.0 0.00929
            AHB2APB Bridge - v1.0 0.0062
            AHB Clock Control - v1.0 0.01922
            The maximum I/Os for this package is , but your configuration has total I/Os.
            The maximum die area for this package is mm², but your configuration has mm².

            Final pin mapping will be based on design layout

            Clock Setting

            Clock Selection System Clk Freq Peripheral Clk
            8.0 MHz

            Run Mode Profile Configuration

            Component Run Mode Op Current (μA) Clock
            Name 1 2 3 4 5 I(D) I(A) (MHz)
            UART (APB) 16.8 0.0 8.0
            UART (APB) 16.8 0.0 8.0
            SPI Master (APB) 2.4 0.0 8.0
            AHB QSPI Flash Interface 2.4 0.0 8.0
            Raptor Power Circuit 0.0 0.0 8.0
            Raptor JTAG Controller 0.0 0.0 8.0
            AHB ROM 0.0 0.0 8.0
            AHB Debug IO 2.4 0.0 8.0
            AHB2APB Bridge 1.6 0.0 8.0
            AHB Clock Control 6.4 0.0 8.0
            Crystal Oscillator (1 - 4 MHz) 0.0 169.6 8.0
            RC Oscillator (1 MHz) 0.0 10.2 8.0
            High Speed SRAM (16kB) 711.7 0.0 8.0
            Arm Cortex M0 578.3 104.6 8.0

            Total Current by Run Mode

            Run Mode Use percentages must total 100%
            Operating Current (mA)
            #1 #2 #3 #4 #5
            Digital (VDD=1.8V) 1.29 1.29 1.29 1.29 1.29
            Analog (VDDA=3.3V) 0.28 0.28 0.28 0.28 0.28
            Run Mode Use (%)

            Power Consumption Estimate Summary

            Operating Current (mA) Stop Mode Standby Mode
            Run (all) Run (weighted) (nA) (nA)
            Digital (VDD=1.8V) 1.34 1.3 480.0 0.0
            Analog (VDDA=3.3V) 0.28 0.3 103000.0 0.0

            SPECIFICATIONS

            None None None
            SoC Design Template raptor
            CPU

            Hardened ARM Cortex M0 microprocessor for embedded applications.

            Memory

            X-Fab 12-bit address x 32 bit data single-port SRAM

            External Clock

            1 – 4 MHz crystal oscillator. 

            Internal Clock

            1 MHz RC oscillator with internal R and C.

            AHB QSPI Flash Interface AHB compatible QSPI peripheral to communicate with external SPI Flash Memory. It is designed for Microchip SST26VF064B Flash memory.
            UART (APB)

            UART interface controller for APB bus.

            UART (APB)

            UART interface controller for APB bus.

            SPI Master (APB)

            SPI master controller for APB bus.


            PACKAGE

            POWER CONSUMPTION ESTIMATE

            Operating Current (μA) Stop Mode Standby Mode
            Run (all) Run (weighted) (nA) (nA)
            Digital (VDD=1.8V) 1.34 1.3 480.0 0.0
            Analog (VDDA=3.3V) 0.28 0.3 103000.0 0.0
            None None None

            Licensing Cost

            0

            Part Cost Estimate

            0

            Die Area

            0 mm²

            0

            Category Violation(s)

            IRQ Violation

            Multiple peripherals share the same IRQ value

            I/O Violation

            Total I/O count exceeds the selected package maximum I/O

            Die Area Violation

            Configuration Die Area exceeds selected package maximum die area

            Peripheral Violation

            Please select a valid peripheral from the dropdown menu