Sebastian Wiebking | https://www.idpro-online.de
Digital test design with simple GPIO control for toolchain testing
This project is intended to implement a closed-loop class-d audio amplifier with 1.8 V power...
Arduino compatible Risc-V Based SOC
SUMANTO KAR | https://www.vlsisystemdesign.com/
This project focuses on design of a Sziklai Pair Amplifier using Google Skywater (sky130)...
NALINKUMAR S | https://www.vlsisystemdesign.com/
This project focuses on design of a Current Starved VCO using Google Skywater (sky130)...
ROHINTH RAM R.V. | https://www.vlsisystemdesign.com/
Two Stage CMOS Operational Amplifier
Matt Venn | https://www.zerotoasiccourse.com
Madhuri Hemant Kadam | http://www.vlsisystemdesign.com/
CMOS OPAMP is Basic building block of analog and Mixed signal circuits. It is used in many...
A Devipriya | https://www.vlsisystemdesign.com/
This project produces a clean GDS - Final Layout with all details that are used to print...
Sameer S Durgoji | https://www.vlsisystemdesign.com/
Design of a 10 Bit Potentiometric Digital to Analog Converter with 3.3V analog voltage, 1.8V...
Charaan Suresh Kumar | https://www.vlsisystemdesign.com/
This project focuses on the design and layout of a Dickson Charge Pump in a 130nm technology...
3v3 comparator with 1v8 output. For possible future uses in ADCs. May also include other related...
Yuki Azuma | https://cpu-dev.github.io/
PicoRV & Jacaranda-8 - It's a hobby heterogeneous processor!
MBIST controller with Row Redundancy Support
Shon Taware | https://vlsisystemdesign.com/
Aims at design of a SRAM cell array with a configuration of 1.8 V operating voltage and access...
Five photodetector layout by sky130 PDK 1. Simple p-n photodiode. 2. Buried double junction...
Basic design to familiarize with this service
Sudoku accelerator module that is capable of running an 'only candidate' pass in 23 cycles and a...
Mohammad Khalique Khan | https://www.vlsisystemdesign.com/
This project produced a clean GDSII Layout with all details that are used to print photomasks...
Abdullah YILDIZ | https://yongatek.com/
YONGA-SERV Accelerator includes the award-winning SERV RISC-V processor with a matrix...
Abdullah YILDIZ | https://yongatek.com/
YONGA-100M Ethernet is based on the implementation of Alex Forencich's 100Mbps Ethernet design.
This submission is for Ibtida-I which was selected for the First MPW Shuttle. Due to the issues...
This projects aims to design an high speed adder based on recursive doubling technique and...
Zain Rizwan Khan
An implementation of the original Ghazi SoC (https://efabless.com/projects/20) hardened using...
Omar Mohamed Saadawy
Voltmeter & Ammeter
Karthik M B
Dadda multiplier is a type of binary multiplier which uses less munber of gates when compared to...
Implements a version of the parallel random-access machine used in theoretical computer science...
Random number generators, PUFs, and resubmission of MPW-1 Softshell.
Manikanta | https://univisiontechnocon.com/
RISC-V Core Based Subsystem
Amro Tork | https://mabrains.com
1V8 LDO Design in Skywaters 130nm
This project is implementation for conversion of 19bit fixed point number to single precision...
SHA/AES accelerator and VGA graphics demo
A attempt to integrate various peripherals like I2C, I2S, UART, SPI, QSPI , JTAG, PWM, GPIO ,...
S Skandha Deepsita
This project is implementation of approximate multiplier published in ACM TODAES journal 2021,...
This project is a light version of the Elpis core, which is a 5-stage pipelined and multi-cycle...
Nicholas R. Smith
ASIC designed to translate input from the Donkey Kong Jungle Beat bongos into PS2 keystrokes.
Test SoC using Coriolis for PnR with nMigen on Sky130
VSDMemSoC is a small SoC including a RISCV-based processor named RVMYTH and an external 1kB SRAM...
This project implements a pre-trained neural network for hand-written digits from MNIST dataset.
The project instantiates an SRAM block in the user project area for testing.
Project instantiates HyperRAM driver for external memory chip (8MB version) and additional...
Reduced version of TreePRAM for faster builds and tests. Not submitting for the shuttle.
Key value store implemented on asic.
This is a Analog to Digital Converter based on the popular SAR architecture. It has 8-bit...
A template SoC for Google sponsored Open MPW shuttles for SKY130
CAN bus controller and teaching-oriented CPU core
Matthew Guthaus | https://vlsida.soe.ucsc.edu/
This project contains a test chip for several OpenRAM memory configurations. The configurations...
Mufutau Akuruyejo | httpS://WWW.vlsisystemdesign.com
VSDBabySoC is a small SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
Philipp Gühring | https://libresilicon.com/
This is a testwafer project with standard cells that were automatically generated by the...
A reconfigurable logic circuit made of identical rotatable tiles.
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process. This project...