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Caravel Plus

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Caravel Plus

Caravel management SoC attached to the largest possible DFFRAM that can fit the user's area. For the RAM related development, refer to DFFRAM

Caravel Integration

Verilog View

The DFFRAM macro is placed on the management area wishbone bus at address (0x30000000). For the memory interface and wishbone bus conversion, refer to Caravel_RAM_24KB_wb

GDS View

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Owner

Mohamed Shalan, Ph.D.

Organization URL

http://efabless.com

Summary

Caravel management SoC attached to the largest possible SRAM that can fit the user's area.

Version

1.00

Shuttle Tags

Open MPW

MPW-1

Tags

MPW-ONE

Open MPW

PicoRV32

SoC

Test Harness