Logo

RAM_Generator

public

RAM Generator from MERL

This repository contains the memories generated by our RAM Generator using sky130 sram as a base model for testing purpose.

Directory Structure

├── verlog                          #   User verilog Directory
│   ├── rtl                         #   RTL
│   ├── dv                          #   Design Verification
│   ├── gl                          #   Gate Level Netlis

The Memories Source Code is avaialable here

├── verlog                               #   User verilog Directory
│   ├── rtl                              #   RTL
|       ├── user_project_wrapper.v       #   User Project Wrapper source file
|       ├── user_proj_example.v          #   User Project Example source file
|       ├── rams                         #   Rams folder
|           ├── ram_256x32_2r1w          #   Ram 256x32 2r1w folder
|               ├── ram_generated_256x32_2r1w.v             #   RAM 2r1w source file
|               ├── ram_generated_256x32_1rw.v              #   RAM 1rw source file
|               ├── sky130_sram_1kbyte_1rw1r_32x256_8.v     #   1KB sram
|               ├── utils.vh     				 #   utils header file

The Design Verification Testbench is available here

├── verlog                               #   User verilog Directory
│   ├── dv                               #   Design Verification
│       ├── BrqRV_EB1                    #   Design Test Directory
│       ├── hex                          #   Hex files folder
│       ├── asm                          #   Assmebly files folder

The synthesized netlist is present here:

├── verlog                               #   User verilog Directory
│   ├── gl                               #   Gate Level Netlis
│       ├── user_project_wrapper.v       #   User Project Wrapper Netlist
│       ├── user_proj_example.v          #   User Project Example Netlist

The hardened macros are placed here:

├── def                                 #    def Directory
│   ├── user_project_wrapper.def        #    User Project Wrapper def file

├── lef                                 #    lef Directory
│   ├── user_project_wrapper.lef        #    User Project Wrapper lef file
│   ├── user_proj_example.lef           #    User Project Example lef file

├── gds                                 #    gds Directory
│   ├── user_project_wrapper.gdz.gz     #    User Project Wrapper gds
│   ├── user_proj_example.gdz.gz        #    User Project Example gds

Testing of Design

Go to verilog/dv/BrqRV_EB1/ directory

  1. Set the GCC_PATH environment variable.
  2. Set the PDK_PATH environment variable.
  3. run the make commad for RTL simulation
  4. run the SIM=GL make command for netlist simulation

If you are collaborating on this project, please click here to access your collaboration files, and click "Accept Share" in the actions column if you haven't done so already.

Owner

hamza shabbir

Summary

This project is for the testing purpose. We wanted to test the memory generated using SRAM as a based model from our RAM Generator.

Version

Version 1

Category

sram

Process

sky130A

Shuttle Tags

Open MPW

MPW-4

Last MPW Precheck

Succeeded

12/30/21 07:39:18 PST

Last Tapeout

Succeeded

12/30/21 08:32:43 PST