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picorF0

public

- CAN bus controller for autonomous vehicles, connected to caravel and with it's I/O and debug interfaces exposed on I/O pins (developed by Natalia Machado)

- picoRF0 - a multicycle CPU core running a simplified RISC ISA (used for teaching, normally on FPGAs). Connected to caravel for memory interfacing and I/O usage
    - can be tied to the CAN bus controller through caravel

- Tiny VGA pong game controller to test I/O interface speed

If you are collaborating on this project, please click here to access your collaboration files, and click "Accept Share" in the actions column if you haven't done so already.

Owner

Anish Singhani

Summary

CAN bus controller and teaching-oriented CPU core

Version

1.0

Category

processor

Process

sky130A

Shuttle Tags

Open MPW

MPW-3

Tags

CPU

Last MPW Precheck

Succeeded

11/14/21 22:13:49 PST

Last Tapeout

Succeeded

11/14/21 23:03:02 PST