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Elpis Light processor

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Authors


¹ Universitat Politècnica de Catalunya (UPC)

 

Project description

This chip is a reduced version of the one developed by the authors during the following courses of the MIRI-HPC master taught in the UPC:

  • Processor Architecture
  • Multiprocessors Architecture
  • Processor Design

Chip layout

Chip description

Elpis is a 5-stage pipelined and multi-cycle in-order processor implemented from scratch based on RISC-V architecture, mixed with some MIPS ideas. However, due to the limitations of the tools this Elpis is lighter than our initial Elpis core. Anyway, the version that we present has the following characteristics:

  • 32 integer registers
  • Special register file
  • Full bypasses
  • Powerful instruction set, mainly based on RISC-V instructions, but with some customed ones
  • L1 instruction and data caches (iCache and dCache)
  • Main memory simulates 5 cycles delay per access, to be more realistic
  • Store buffer
  • Support to exceptions
  • I/O support
  • Simulated virtual memory support (NO TLBs!)

Pipeline diagram

ISA

The supported instructions by Elpis are: ADD, SUB, MUL, LDB, LDW, STB, STW, BEQ, JUMP, IRET, MOVE, TLBWRITE, ADDI, OR, ORI, AND, ANDI, XOR, XORI, SLL, SRL, SRA, SLLI, SRLI, SRAI, BGE, BLT, BNE, MOVR, ECALL, READ, PRINT. The instruction set encoding is mainly based on RISCV32, but there are some differences respecting the pipeline management where we present new instructions not existing in RISC-V:

  • IRET: It is always codified as 0x0000007F, sets the PSW to 0 (user mode) and jumps to the PC that RM0 holds. This instruction is only permitted to execute if PSW=1 (privileged mode).
  • JUMP: Jumps to the address that the given register points to. For example, the instruction semantics could be jump x9, where its decoding will result in an OPCODE [6:0] = 1101111 and destination register = [19:15]. As for the rest, the other bits are ignored.
  • MOV: Used to move register data from special registers to regular ones. For example, the instruction semantics could be mov x7, rm2, where its decoding will result in an OPCODE [6:0] = 0101111, funct7 [31:25]= 0000000, source register (special register) = [21:20] and destination register (regular register) = [11:7]. As for the rest, the other bits are ignored.
  • MOVR: Used to move register data from regular registers to special ones. For example, the instruction semantics could be movr rm4 x15, where its decoding will result in an OPCODE [6:0] = 0101111, funct7 [31:25] = 0000001, source register (regular register) = [21:20] and destination register (special register) = [11:7]. As for the rest, the other bits are ignored.
  • ECALL: It is an instruction to call the operating system, so user-mode has to be enabled. However, at the moment, there are only supported two different calls. If it is performed ecall 6 is codified as 0x00600073, otherwise if is an ecall 7 is codified as 0x00700073. The code 6 is used in case we want to send data to PicoRV, and the code 7 is used in case we want to receive data from PicoRV.
  • PRINT: This instruction sends into the PicoRV whatever is inside the special register rm4, and it is always codified as 0x0200007D. However, this instruction is only legal if privileged mode is enabled. On the other hand, if user mode is enabled it should be executed through an ecall instruction (ecall 6), which would result in an equivalent functionality.
  • READ: This instruction receives a value from PicoRV, and it is always codified as 0x0400007D. However, this instruction is only legal if privileged mode is enabled. On the other hand, if user mode is enabled it should be executed through an ecall instruction (ecall 7), which would result in an equivalent functionality.

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project layout image
project layout image
Layout Image
Owner

Aurora Tomás Berjaga

Summary

This project is a light version of the Elpis core, which is a 5-stage pipelined and multi-cycle in-order processor based on RISC-V architecture, mixed with some MIPS ideas.

Category

processor

Process

sky130A

Shuttle Tags

Open MPW

MPW-3

Tags

CPU

MIPS

RISC-V

Last MPW Precheck

Succeeded

11/14/21 18:10:29 PST

Last Tapeout

Succeeded

11/14/21 22:55:23 PST