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Caravel_RISCV_OSU

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OSU RISC-V Caravel

This is an implementation of a single-cycle RISC-V processor inside of the Caravel test system for use in the SkyWater 130nm PDK.

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Owner

James Stine

Summary

Caravel_RISCV_OSU is an implementation of a single-cycle RISC-V processor inside of the Caravel test harness intended for use with the SkyWater 130nm PDK.

Version

0.1

Category

Test Harness

Process

SKY130

Shuttle Tags

Open MPW

MPW-1

Tags

Open MPW

Test Harness

RISC-V

MPW-ONE

Last MPW Precheck

Failed

12/16/20 14:44:12 PST