OSU RISC-V Caravel

This is an implementation of a single-cycle RISC-V processor inside of the Caravel test system for use in the SkyWater 130nm PDK.

Layout Image
Owner
James Stine
Description
Caravel_riscv_osu Is An Implementation Of A Single-Cycle Risc-V Processor Inside Of The Caravel Test Harness Intended For Use With The Skywater 130nm Pdk.
Version
0.1
Category
Test Harness
Process
Sky130
Tags
['open Mpw', 'test Harness', 'risc-V', 'mpw-One']