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Caravel

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N5 SoC for Caravel

The repo contains the N5 SoC integratin with the Caravel chip. For the SoC related development, refer to N5 SoC

Caravel Integration

Verilog View

The SoC utilizes the caravel IO ports and logic analyzer probes. Refer to user_project_wrapper.v and this.

GDS View

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Owner

Mohamed Shalan, Ph.D.

Organization URL

http://efabless.com

Summary

NFive32-Based SoC to validate several open-source projects and IPs.

Version

1.00

Tags

MPW-ONE

Open MPW

Test Harness