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Serial RISC V (SERV)

public
Owner

R.Thanga Gnana Jenef

Summary

SERV is a bit-serial CPU which means that the internal datapath is one bit wide. . For each instruction, data is read from the register file or the immediate fields of the instruction word and the result of the operation is stored back into the register file. Reading and writing memory is handled through the memory interface module.

Category

processor

Process

sky130A

Shuttle Tags

SSCS-21