In this proposal, the entire GPS baseband functionality is realized using a combination of custom designed logic functionality GPS Engine (ASIC portion) and the on chip RISCV microprocessor to provide the complete position fix starting from the digitized IF input bits. The signal processing operations in the baseband comprise of dispreading and data demodulation performed on six identical channels followed by psuedo range, and position fix computation. The major part of the signal processing operations for the six channels are carried out in the GPS Engine and the low frequency control tasks and position fix computation tasks are carried out in the RISCV processor.
The operation of the proposed system can be understood with help of Fig.1, Fig.2, and Fig.3. The baseband operations to be carried out in each channel of the receiver include (i) the coarse acquisition which involves searching for visible satellites and estimating their delay with an uncertainty of less than half a chip, and estimating their Doppler with and uncertainty of nearly 250Hz (ii) reducing the Doppler uncertainty from 250Hz to less than 10Hz in a Frequency Locked Loop (FLL) , (iii) Reducing the code delay from half a chip to much less than one tenth of a chip and continuously tracking the same in a Delay Locked Loop (DLL) (v) Further reduce the Doppler uncertainty from 10Hz to less than 1Hz and continuously track the carrier in a digital Costas Loop and finally (iv) Data demodulation of the 50bps data. These tasks are all predominantly carried out in parallel in six channels in the GPS Engine block shown in Fig. 1, with aiding from the onchip RISCV processor in the low rate control and computational tasks. In the RISCV processor, the demodulated 50bps data from the visible satellites are collated together and the solution for position fix is computed.
The only logic blocks that need to be realized in in each channel of the ASIC portion of the GPS Engine are (i) Gold Code generators with the Prompt(P) , Early(E) and Late (L) versions with the latter two being used for the DLL (ii) Number Controlled Oscillators (NCOs) for code clocks for code tracking as well as carrier sine and cosine generation for digital downconversion and carrier tracking (iii) multiple integrate dump filters (accumulators) to perform the correlation operations. For each channel, these logic blocks are essential and sufficient to perform all the signal processing operations of coarse acquisition, FLL, Costas Loop tracking and Delay Locked Loop tracking. These blocks are shown in the form of a block diagram in Fig.2.
The communication interface between the ASIC portion of the GPS engine and the RISCV uses the 32 bit wide on chip bus. Along with the additional memory blocks and I/O interfaces, the complete block diagram is shown in Fig.1.
Matlab code corresponding to the receiver architecture of Fig.2 has been developed has been tested extensively with real time GPS signals captured at IF and multiple bit precisions for each of the blocks. The proposed receiver architecture has also been tested over many years with realizations in multiple Cyclone, Stratix, Virtex and Zynq FPGAs. The FPGA versions have been tested by interfacing them to the GP2015 RF Front End as well as AD9364 programmable RF front end for SDRs. So for the proposed GPS Engine, only codes that have been verified over many years in hardware will be used. This work is carried out solely by students, executed over many years by with contributions from multiple batches of students. The present proposal will also be executed by current second and third year undergraduate students with help from alumni. With suitable modifications in the RF front end module, the proposed GPS Engine can also be used for the IRNSS (L1 band and S band) which also as the same signal structure as that of GPS. Once the digital backend is validated, in the next open source tool and tape out opportunity, another student team would propose the design GPS RF Front End ASIC. Once this GPS platform is ready, optimizations for power, area and integration with other sensors for IOT and other applications will be taken up subsequently.
(Associated with Dept. of ECE, College of ENgg., Guindy, Anna Univ. Chennai, INDIA)
Dr. P.V.Ramakrsihna, Coordinator
The present project would design a custom GPS Baseband Engine (digital ASIC portion) which, in conjunction with the onchip RISC V microcontroller, would provide the complete position fix starting from the digitized IF signal obtained from an external RF front end