ASICs are useful for fast machine learning inference, especially in the field of biomedical engineering, given the prevalence of image analysis in medicine. As inference on images requires more computational power than parameters such as age and height, a dedicated device (ASIC) to analyze images, especially in real-time, could see extensive use.
Applications could include analyzing the motor movements of Parkinson’s disease patients , detecting abnormalities in real-time using ultrasound or x-ray , determining brain state using fMRI , and analysing ECG readings . For these applications, specialized circuits are appropriate.
Neural networks (NNs) are consistently at the cutting edge of image recognition. These machine learning algorithms are modeled after the neurons in the brain and use a large number of neurons to capture complex features in the data.
Convolution neural networks (CNNs) in particular have proven to be the ideal architecture for image recognition because their design takes into account the relationships between pixels neighboring one another; a representation of such a CNN is depicted below .
In general, neural networks typically have large numbers of parameters and operations, resulting in large memory and computational requirements. This incentivizes companies to make ICs specifically for machine learning, such as Google’s tensor processing unit (TPU) and NVIDIA’s Turing Tensor Cores.
As machine learning research accelerates, application-specific ICs will see their niche as compact, energy efficient, and fast devices to run machine learning algorithms on the edge, prompting the coining of the term Tiny Machine Learning or TinyML, machine learning where power and computational resources are minimized.
Due to the nature of the Caravel and the Skywater SKY130 PDK in particular, we will first design a proof-of-concept ASIC that runs inference on the MNIST handwritten digit dataset using a modernized LeNet-1 (max pooling instead of average pooling, Adam optimizer, etc.).
This dataset is one of the simplest image datasets, consisting of 28x28 grayscale pixels, and LeNet is one of the simplest forms of a CNN while still yielding 98+% accuracy on MNIST. There are only 2600 parameters, so it should be compatible with Caravel’s memory requirements.
If the die area and Caravel harness seems capable of supporting models larger than LeNet, or if we determine that external memory can mitigate these restrictions, we will implement SqueezeNet for image classification  or the You Only Look Once (YOLO) Real-Time Object Detection algorithm .
TensorFlow will be used for prototyping the particular network architecture used and obtaining expected accuracies for the model since we are most familiar with TensorFlow. Tensorflow has the MNIST database in a convenient reference. DNNWeaver  uses the Caffe format to specify model architectures, so we will translate the model architecture into Caffe and supply our own parameters for the model calculated from training. DNNWeaver then uses this model architecture to produce Verilog to be hardened, which we will adapt to Caravel. If we determine Caravel suitable for larger models, we will use Darkflow to interface with get the weights of pretrained models from Darknet. Darkflow is already a dependency of DNNWeaver for importing weights.
The diagram above shows the information and development workflow for TIDENet. There are three main stages. First, the weights and structure of our neural network (for LeNet-1 on MNIST or a larger model off of Darknet) are used as parameters for DNNWeaver 2.0, which generates FPGA-oriented Verilog. We then translate this Verilog to ASIC-compatible verilog. Second, we harden our design using OpenLANE, which is the most suitable for an open-source design on Caravel. This results in the RTL Verilog code being converted into GDSII instructions appropriate for the Caravel harness. Finally, this is passed through the Caravel and fabricated.
Cole Blackman (Undergraduate), Justin Zhang (Undergraduate), M. Ceylan Morgul (Ph.D. student)
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TinyML Image Detection on the Edge with neural Networks, or TIDENet, is an ASIC written in Verilog using DNNWeaver 2.0, the Google SkyWater PDK, OpenLANE, and Caravel.
Deep Neural Networks