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Oscillator based read-out circuit for LVDTs

Linear Variable Differential Transformers (LVDT’s) are inductive sensors that are most commonly used in any applications where there is a need for converting mechanical displacement into electrical signal. At present, there are many commercial signal conditioning ICs available for LVDT. The present work proposes a completely alternative oscillator based procedure for displacement measurement.

Motivation for time domain processing in LVDT signal conditioners

            All of the commercially available signal conditioners for LVDT use voltage domain signal processing to extract the position information [1-5]. In all of these, the primary coil of the LVDT is excited by a highly stable precision oscillator, and the voltage amplitudes from the secondary coils are measured using complicated circuitry. However, the author of this present proposal along with the other authors had proposed a far simpler technique for displacement measurement using time domain signal processing [6]. The present work deviates significantly from the conventional methodology of considering the LVDT as a transformer and adopts a simple method that treats the secondary coils as forming an unknown differential inductance that is then measured. The principle of oscillator-based measurement has been widely utilized in many resistive and reactance sensors .But treating the LVDTs as reactance sensor and utilizing the oscillator-based methodology have been attempted first in [6].

So, the present proposal discusses the realization of the oscillator based measurement procedure that can give comparable or better accuracies in comparison with the existing signal conditioners for LVDT.

Oscillator based read-out circuit for LVDT

A simple and novel alternative method for LVDT signal conditioning is demonstrated in [6]. In the proposed method, the primary coil is left unused and hence avoids the use of low distortion sine wave oscillators for primary coil excitation and the associated phase compensation circuitry. The read-out circuit uses the secondary coil of an LVDT as part of a Colpitts oscillator along with a frequency counter to derive the position information. The proposed Colpitts oscillator prototype is realised using discrete BJT transistors and an FPGA is used for frequency counting. The resolution of the experimental setup reported was shown to be limited by the reference clock frequency used. It was shown that by using the max clock frequency supported by the FPGA (400MHz), the resolution obtained is about 14bits, and by averaging 1000 samples, the resolution was shown to be increased to 16 bits. A compact CMOS IC for LVDT signal conditioning using oscillator based method is not yet reported in the literature. This is part of a PhD research work. Therefore, as a part of the research work, this proposal attempts to design a CMOS based signal conditioner with an on-chip frequency counter in order to overcome the above said disadvantages.

Circuit details of the proposed work

            From the above description, it is clear that the proposed work is in need of three major circuit blocks. They are (a) CMOS based oscillator for converting the LVDT inductance to frequency information, (b) a slope amplifier to convert the inductance information suitable for time domain signal processing and (c) a Frequency to Digital converter (FDC) to derive the frequency information in digital domain. Figure 1 below shows the complete circuit blocks with its schematics. Each of these circuit blocks are described in detail below

Colpitts oscillator

            The circuit schematic of the single ended common base colpitts oscillator is shown in Figure 1. In this circuit, L1, C1 and C2 constitute the tank circuit of the Colpitts oscillator, and L1 and R1 together represent one of the secondary coils of the LVDT. For the LVDT used, the typical value of secondary inductance when the core is at the null position is in the order of 10mH and the value of R1, is 68 Ω. LVDTs are usually operated at low frequencies (2KHz -10KHz). So in order to make the coils resonate around 10KHz, the combination of C1 and C2 capacitance should be chosen in the order of 25 nF. Owing to the size of the LVDT inductance and the resonant capacitance, these should be implemented off chip. The bias voltage VA and VB can be derived with the help of a bias generator circuit or using a simple potential divider from the supply.

Figure 1. CMOS based read-out for LVDT

Slope amplifier

A slope amplifier/comparator is typically used at the input of a frequency counter for precise frequency measurement and it follows the Colpitts oscillator. A voltage follower circuit is used at the output of the Colpitts oscillator to avoid any loading effect on the oscillation frequency by the slope amplifier. Slope amplification process adds noise due to noise folding.

Two existing works [7] and [8], that addresses this issue of minimum noise addition due to slope amplification have been diligently studied. Both these works suggest that the slope amplification has to be carried out in multiple stages. [7] and associated references reports a slope amplification of a 30 kHz signal achieved using multiple stages of Gm-C integrators. It suggests an effective way of designing the Gm-C integrators such that the noise folding from aliasing that is caused during slope amplification will be minimum. This technique is considered for the present work as it is appears suitable to be realised in CMOS technology. The circuit schematic of a multi stage Gm-C integrator is shown in figure 1. A slope-amplifier must be designed using a multistage Gm-C integrator such that it can handle a rise time in the order of 1ns to the TDC with a jitter contribution of at least around 1/10th of the jitter contribution from the oscillator.

Frequency to Digital converter

            As said earlier, the counter based frequency measurement [6] requires higher clock frequency in order to achieve higher resolution. Another alternative is to use the ∑-Δ Frequency to digital converters. Oversampling is commonly used in sigma-delta ADCs to achieve very high resolution even with a coarse converter. Because of its significant advantages, the above FDC architecture is chosen for this work [9]. The functional diagram is shown in Fig. 1. It consists of a charge pump and associated gating logic that constitutes a Phase detector, a 2-b ADC, a block, a digital constant adder, a 4-b counter, and a pulse stretcher. Two events control the timing: 1) transition of input from low to high and 2) transition of the “Carry” signal from low to high. The 4-b counter is driven by an 80 KHz external clock, and the “Carry” signal goes high on its terminal count. In normal operation, the Q output of the flip flop goes high when the input goes high. This causes the positive current source in the charge pump, Ip to be connected to the capacitor. This current source remains connected to the capacitor until the “Carry” signal goes high, at which time it is disconnected from the capacitor. The negative current source, In  is connected to the capacitor for a fixed duration each time the “Carry” signal goes high. Two 80 MHz clock cycles after the “Carry” signal goes high, the counter is loaded with a number obtained by filtering the ADC output. This effectively sets the time until the next “Carry,” that closes the feedback loop. The output of this modulator is then fed to a digital low pass filter to derive the frequency information. This can be realized using the onchip RISC processor.

Target specification

The main target is to achieve a resolution comparable to the state of art commercially available LVDT signal conditioners with a much simpler architecture.

Full scale frequency range: 7-11 KHz (corresponding to typical LVDT displacement range of 0-25mm)

Frequency measurement resolution: 15-17 bits (same as LVDT displacement resolution)

Typical measurement update rate : 100ms

References

[1]  Analog Devices. LVDT Signal Conditioner AD598. Accessed:Jan. 15, 2018. [Online]. Available:www.analog.com/media/en/technicaldocumentation/data-sheets/AD 598.pdf

[2] Analog Devices. LVDT Signal Conditioner AD698. Accessed:Jan. 15, 2018. [Online]. Available: www.analog.com/media/en/technicaldocumentation/data-sheets/AD 698.pdf

[3] Texas Instruments. (Dec. 2016). PGA970 LVDT Sensor Signal Conditioner.[Online]. Available: www.ti.com/lit/gpn/pga970.

[4] Analog Devices. (2015). Circuit Note CN-0371. [Online]. Available:www.analog.com/media/en/reference-designdocumentation/reference/CN0371.pdf

[5] R. Poley, “Signal conditioning an LVDT using a TMS320F2812 DSP,” Texas Instrum., Dallas, TX, USA, Appl. Rep. SPRA946, Aug. 2003. [Online]. Available: www.ti.com/lit/an/sprs946/spra946.pdf

[6] G. Vinodhini, S. Aniruddhan, B. George, J. D. Devi, and P. V. Ramakrisha, “Performance analysis of oscillator based read-out circuit for LVDT,” IEEE trans. on Instrumentation and measurement, Vol.68, Issue 4, April 2019.

[7] Igor Izyumin, et.al., “A 7ppm, 6°/hr frequency-output MEMS gyroscope”, IEEE International conference on MEMS, Jan, 2015.

[8] Oliver Collins, “The Design of low jitter Hard Limiters”, IEEE Transactions On Communications, Vol. 44, No. 5, May 1996.

[9] Ian Galton, “Analog input digital Phase-locked loops for precise frequency and phase demodulation”, IEEE trans. on circuits and systems- II: Analog and digital signal processing, Vol. 42, No.10, October 1995. 

Owner

Vinodhini G. Edward

Summary

This project aims at designing an Oscillator based read-out circuit for LVDT using time domain signal processing, unlike the commercially available signal conditioners.

Category

sensor

Process

sky130A

Shuttle Tags

SSCS-21