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RISC-V Bare Minimum MCU

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Description

As someone working in Embedded Product development, designing low-cost devices can become challenging, where the limiting cost depends on the price of microcontrollers. Also, another factor is the cost involved in programming. As the MCU manufacturers put in more complex IP cores in the design, and then multiplexing them with GPIOs, it becomes more difficult to program them by an inexperienced programmer, thus increasing the cost of programming. And in most of the low-cost applications (home appliances, use and throw type devices etc), most of these complex cores are not even required. Only digital I/Os suffice for the application. Hence, there is a need for low-cost, low-complexity MCUs.

Design Goals

The goal is to design a bare-minimum microcontroller. In any microcontroller for low-cost applications, the essential requirements are for GPIOs, Timers, and sometimes a USART is handy. For most applications, 2 Timers are more than enough, and 32 GPIOs can suffice.

Design Overview

The design has a 32-bit RISC-V CPU, a Flash, and SRAM, and 2 GPIO ports, all interconnected with AHB bus. Also, it has a USART module, and 2 32-bit Timer Modules, interconnected with APB bus, and communicate to AHB bus using a bridge. To program and debug the microcontroller, JTAG is incorporated.

Block Diagram

Owner

Prabhat Narang

Summary

MCus today have become so general-purpose, that they incorporate many IP modules (Like multiple UARTs, SPIs, I2Cs, ADCs, etc). The goal is to design a bare minimum, all-digital MCU such that the price and complexity associated with embedded designs can be reduced.

Category

processor

Process

sky130A

Shuttle Tags

SSCS-21

Tags

Digital

MCU

RISC-V