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Motivation

Sophistication and complexity of artificial intelligence and its demand in healthcare applications have sparked our interest in developing efficient methods to design real-time biomedical systems for detection and prediction of symptoms of complex diseases or abnormalities. Sleep apnea is one of the leading causes of sudden death around the globe, particularly in neonatal infants and adults aged over 50 years and the methods of pre-screening and detecting such abnormality are still in progress. Various sensor technologies adopting artificial intelligence in detecting and predicting of sleep apnea have been developed in recent years leading to the rapid progress in biomedical research. Based on multiple literature reviews, we have developed the idea of integrating machine learning models onto hardware and designing a real-time sleep apnea detection system. By using our proposed energy efficient design technique called DeepSAC (Shift-Accumulate Based Deep Learning Hardware Model), we are introducing a compact, energy efficient, smart, and portable system capable of detecting apnea in real-time.

Description

In this project we propose to design a feedforward neural network (FNN) model based digital signal processing circuit which is capable of detecting sleep apnea. The design-model takes in pre-processed digital data from two types of biomedical sensors: 1) single channel ECG sensor data and 2) blood oxygen saturation level: SpO2 to detect sleep apnea. Figure.1 showcases the block diagram of the overall system, and the red block indicates our targeted design element. The novelty of this design is the use of digital shifters instead of multipliers to reduce power consumption by 13x times [1]. The proposed DeepSAC technique is a significant improvement compared to the design method introduced in [2]. According to Figure.1 our proposed pre-trained FNN inference module takes in digitally processed input dataset from the two sensors and results in binary output (1: sleep apnea and 0: absence of sleep apnea/normal condition). 

Block Level Diagram of the Proposed Sleep Apnea Detection System

Figure 1: Block Level Diagram of the Proposed Sleep Apnea Detection System

The FNN model was trained using data collected from open-source ApneaECG database from PhysionetBank [3] and a 3-hidden layer (8-6-4) model was developed which successfully detected apnea with over 86% accuracy. ReLU activation functions were used in the hidden layers and sigmoid function was used in the output layer. Full model parameters (fixed weights and biases) were extracted and used in designing the digital hardware model. A typical neural network hardware accelerator uses multiply-accumulate (MAC) operation as its neuron unit which consumes majority of the power in the design. The proposed  DeepSAC method eliminates this high-power consumption issue by replacing multipliers with shifters. Each value of the of the weight  extracted from the network layers is conditioned to the power of 2 and designed into n-bit shifters (n is the assigned bit number). The weight values within a certain range are replaced with their corresponding shifters. For example, for weights with value 17 instead of multiplying input data with 17 a 4-bit shifter has been used shifting the input data to 4-bits which is equivalent to multiplying it with 16. For performance and power consumption analyses we designed the entire model onto field-programmable gate array to study the reports and justify the proposed low power design scheme. Figure. 2 showcases the IP block diagram of the complete FNN model and Table I presents the hardware utilization and the power consumption reports. The input layer takes in 9-bit integer data where the most- significant bit (MSB) is the sign bit. 

IP Block Diagram of the 3 Layer Feedforward Neural Network Embedded Digital Hardware Design on FPGA.

Figure 2: IP Block Diagram of the 3 Layer Feedforward Neural Network Embedded Digital Hardware Design on FPGA.

Table 1: Power Consumption and Hardware Utilization Report on FPGA.

Power Consumption Watt(W)

Hardware Utilization

Number of Elements
Signal 2.364 LUT 114
Logic 2.781 Bonded IOB 29
I/O Port 8.733 Registers 171
Dynamic Power 13.879 Buffer  1
Total Power 14.269 Slices 60

Due to the shifters acting as the values of the weights there were no usage and utilization of SRAMs nor DRAMs in the digital design.

Design Goal

The goal of this project is to design the classification block of the sleep apnea detection model on CMOS integrated circuit platform and study the power consumption rate of a machine learning inspired digital circuit design. We are predicting that the power consumption rate of the IC-chip will be no larger than 50uW. Successful design, analysis and fabrication of the proposed circuit will open new doors in future development and design of low-power, smart and wearable biomedical systems.

Schematic

The schematic diagrams of the major components used in creating the digital signal processing block is shown in figure 3 below.

Schematic of components

Figure 3: Schematic diagrams of the major component used. (a) The 9-bit Adder, (b) n-bit Shifter (c) Sigmoid Activation Function (d) ReLU Activation function. 

Figure 4. showcases the last hidden layer schematic of the 3-layer FNN model.

 Output Schematic Layer

Figure 4: Hidden output layer of the trained Feedforward Neural Network model. 

Reference:

  1. M. M. Hossain, O. Hassan, D. Parvin, M. Cheng and S. Kamrul, “An Optimized Hardware Implementation of Deep Learning Inference for Diabetes Prediction”, IEEE International Instrumentation and Measurement Technology Conference (I2MTC), 2021.
  2. A. Hazarika, A. Jain, S. Poddar and H. Rahaman, “Shift and Accumulate Convolution Processing Unit,” TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON), pp. 914-919, 2019.
  3. Goldberger, L. Amaral, L. Glass, J. Hausdorff, P. Ivanov, C. Mark, H. E. Stanley, “PhysioBank, PhysioToolkit, and PhysioNet: Components of a new research resource for complex physiologic signals.” Circulation [Online]. 101 (23), pp. e215–e220, 2000

Team Members:

  1. Syed Kamrul Islam: Team Advisor
    • Professor and Chair, Dept of EECS, University of Missouri
  2. Omiya Hassan: Team Leader
    • Graduate Student, Dept of EECS, University of Missouri
  3. Riley Jackson: Member
    • Undergraduate Student, Dept of EECS, University of Missouri
  4. Dilruba Parvin: Member
    • Graduate Student, Dept of EECS, University of Missouri

 

Owner

Omiya Hassan

Summary

Our ultimate goal is to design a smart and wearable sleep apnea detection system capable of detecting apnea in real-time. We have developed a unique method to embed trained machine learning/AI models into an energy efficient hardware which eliminates the necessity of utilizing large memory sizes for biomedical signal processing. The objective of this project is to design and fabricate the digital signal processing circuit part of our sleep apnea detection system based on a shifter-based trained feedforward neural network model.

Category

acc

Process

sky130A

Shuttle Tags

SSCS-21

Tags

ACCELERATOR

RISCV

SSCS-21