Openlane RTL to GDSII flow implemented works well for digital synthesis and chip assembly for the test case picorv32 RISC V core.The project implements the RTL to GDSII flow in the openlane tool using RISC V as the test case which is an open standard instruction architecture. Here RISC V implementation is the specification and picorv32 is the RTL implementation of the specification. The methodology was implemented using SkyWater and open source PDK. The results at various stages are steamed out using klayout and
finally GDSII file is obtained that the Foundries accept for the manufacture of ASICs.
The design flow performs the full ASIC implementation of the design from RTL to GDSII. The flow includes various stages- synthesis, floorplanning, clock tree synthesis, routing and physical check like DRC, LVS and antenna checks.The implementation uses Picorv32, a CPU core as a test case