A pipelined-flash ADC architecture and an encoder (DCVSPG encoder) for high-speed flash CMOS ADC is proposed. The pipelined architecture achieves high data throughput and high speed by incorporating pipelined clocked T/H and clocked DCVSPG encoders.
The flash ADC uses a differential architecture in designing the comparator to minimize the input-offset voltage error. The comparator uses the technique of generating the reference voltages internally and eliminating the use of the resistor ladder circuitry.
As a result, improvements on the nonlinearity error and power saving are achieved. The pipelined flash ADC offers a data conversion rate of 2.5 GSPS while maintaining low power consumption, which makes it suitable for SoC applications.
FFT tests with input signal frequency up to 1 GHz prove proper operation over a wideband frequency range. The DCVSPG encoder overcomes the speed limitation of the ROM encoder which has been a bottleneck of high-speed ADCs
VDD: 1.2 V
VLSB = 0.025V
Sampling Rate: 2.5 GSPS
Input Signal Frequency: Upto 1GHz
Power <= 25 mW
Cascade Current Source:
M. Wang, C. H. Chen and S. Radhakrishnan, "Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS," in IEEE Transactions on Instrumentation and Measurement, vol. 56, no. 3, pp. 1064-1073, June 2007, doi: 10.1109/TIM.2006.887404.
1. Aditya Sharma (Lead Designer)
2. Vatsal Dixit
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The proposed ADC is pipelined and mainly consists of three stages: 1) Track-and-hold (T/H) 2) Differential comparator 3) Differential cascode voltage switch with pass gates (DCVSPG) encoder. The T/H uses a current-mode dual-array structure to reduce the aperture jitter for high-input signal frequency. The differential comparator eliminates the use of the resistor ladder circuit by generating the reference voltages internally. The DCVSPG encoder has a full output signal swing and compact logic design style of pass gate circuits, which makes it suitable for high sampling frequency.