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Multiplication and Division Unit (MDU) as a co processor with many SERVs

Description: This project is aimed to design an ASIC version of Multiplication and Division Unit or M-extension of the RISC-V so that it can be integrated with many RISC-V CPU(s) (SERV this time) as a co-processor.

The MDU will hold the logic for entertaining 8 instructions of RISC-V M-extension. Different algorithms can be applied to obtain the optimized area or speed. Instruction list is given below:

  • MUL
  • MULH
  • MULHSU
  • MULHU
  • DIV
  • DIVU
  • REM
  • REMU

Design Goal: The purpose of this MDU is to provide open-source silicon proven M-extension of RISC-V.

Tools: Open-Source: OpenLANE, Verilator, iVerilog, EDAlize

Language: Verilog

Git URL: https://github.com/zeeshanrafique23/serv-mdu.git

Target Performance: The target performance will be tested after integration of as many SERV CPUs with one MDU, the overall performance will absolutely decrease by increasing the SERV cores.

Block Diagram:

Figure: Multiplication and Division Unit (MDU) with many SERVs

Refernces: SERV by Olof Kindgren, https://github.com/olofk/serv/ 

Team Members: Zeeshan Rafique, Olof Kindgren, Dr. Ali Ahmed, Dr. Roomi Naqvi

Owner

Zeeshan Rafique

Organization URL

https://github.com/merledu

Summary

This project is aimed to design an ASIC version of Multiplication and Division Unit that can be integrated with many RISC-V CPUs (SERV this time) as a co-processor. The purpose of this MDU is to provide open-source silicon proven M-extension of RISC-V.

Version

v0.01

Category

processor

Process

sky130A

Shuttle Tags

SSCS-21

Tags

M_extension

RISCV

SERV