YiFive SOC Integrated Syntacore SCR1 Open-source RISC-V compatible MCU-class core + 8 bit SDRAM Memory Controller + Quad SPI. Both Risc V and SDRAM controller are silicon-proven IP.
YiFive SOC Integrated Syntacore SCR1 Open-source RISV-V compatible MCU-class core. It is industry-grade and silicon-proven IP. Git link: https://github.com/syntacore/scr1
Due to number of pin limitation in carvel shuttle, YiFive SOC integrate 8bit SDRAM controller. This is a silicon proven IP. IP Link: https://opencores.org/projects/sdr_ctrl
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32 Bit Risc SOC Design with Quad SPI , 8 bit SDRAM Controller , UART, I2C Master and USB 1.1 Host
01/12/22 00:05:50 PST
01/12/22 02:38:38 PST