Tag results for: skills

Kranthi Kumar Pamarthi

I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.

SKILLS

Magic CAD | Matlab | Netgen | ngspice | Octave | Python | System Verilog | Tcl/Tk | Verilog | VHDL | perl |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Circuits: Filters | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | System: FPGA Programming |

Armagan ERGUN

SKILLS

Cadence Encounter | Cadence Virtuoso | Eagle CAD | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Belal RAFFED

SKILLS

Analog CMOS CIrcuit | C/C++ | CIrcuit Design | Eagle CAD | Electric CAD | Matlab | ngspice | Object Oriented programming | PCB Design and Verification flow | Perl Scripting | Real Time Programming | RTL Simulation | Software Developer | System Verilog | Tanner L-Edit | Unix/Linux environments | Verilog | VHDL | VLSI/ASIC and SOC Development |

AREA OF EXPERTISE

Analg-ADC | Analog IC Design | Analog-ADC | Analog-Layout | Analog-Simulation | CAD: Scripting | Circuits-Microcontrollers | Digital-RTL | Digital-Verification | SOC-DV | System-Bring up | System-FPGA Emulation | System-PCB | System-Signal Integrity | System-Test Equipment |

Zaid Abukhalaf

SKILLS

C/C++ | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers |

Mauricio De Carvalho

SKILLS

C/C++ | Cadence Encounter | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Business: Design Services | Circuits: Microcontrollers | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming |

Daniel J Wisehart

More than 25 years in FPGA design

SKILLS

C/C++ | Perl | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | SoC: Floorplanning | System: FPGA Programming |

Praneeth

SKILLS

Cadence Encounter | Cadence Virtuoso | Hercules | Perl | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Memory | Circuits: Power Management | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning |

Saravanan Nanthakumar

I am a Master Degree holder in VLSI Design. I am interested in Analog Circuit Design.

SKILLS

C/C++ | Electric CAD | Magic CAD | Matlab | ngspice | Octave | Python | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching |

Djamel DELLAA

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Eagle CAD | SPICE Opus | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Verification | Digital: RTL | Digital: Synthesis |

Lefteris Kampianakis

SKILLS

Cadence Virtuoso | Eagle CAD | Matlab | Python | Software Developer | Spectre | VHDL | C | Java |

AREA OF EXPERTISE

Academic: Research | System: PCB |

Venkata Nitheesh Kumar Reddy Kethu

SKILLS

C/C++ | Eagle CAD | Matlab | Octave | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Circuits: Filters | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Samuel dos Santos Delgado

SKILLS

C/C++ | Magic CAD | Octave | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Circuits: Signal Processing | System: FPGA Programming | System: PCB |

Salman Sheikh

Senior Design Engineer at NASA-Goddard., Greenbelt, MD

SKILLS

Eagle CAD | Python | Software Developer | Tcl/Tk | Verilog | VHDL | C |

AREA OF EXPERTISE

System: FPGA Programming |

Mohammed Essam Abd El Samee Soliman

I works as junior physical design engineer and I have passion in VLSI field specially in digital IC design. I have experience in writing RTL, test benches and in PnR flow.

SKILLS

Leadership | Matlab | Perl | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Eduardo Augusto da Costa

Eduardo is an Electrical Engineer engaged in hardware development with a true passion for developing and enhancing applications. While at university, he worked in a variety of projects, from VHDL in a SOC project, to a PCB for a power circuit, and even web interfaces for electronic devices network connected. He allies his technical background with great communication skills. He is used to and is passionate about working in diverse cultural environment as was his period as an international student in Japan. He also got a certification in in Digital Integrated Circuit Design and Project Flow with Cadence tools (IC Brazil Program). Currently he works at HT Micron, and is interested in positions related to chip design, hardware design, embedded software development and similar areas.

SKILLS

C/C++ | Cadence Encounter | Eagle CAD | Matlab | Octave | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Peter Atkinson

SKILLS

C/C++ | Cadence Encounter | Matlab | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Kenneth Jose Rojas Rodriguez

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Python | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Circuits: Communication | System: PCB |

Momen seliem

SKILLS

Calibre | Hercules | Magic CAD | Matlab | Perl | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing |

Stephan Ahles

SKILLS

C/C++ | Cadence Virtuoso | Eldo | Electric CAD | Leadership | Matlab | ngspice | Octave | Python | SKILL | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Marketing | Business: Sales | CAD: Scripting | Circuits: Communication | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis |

Bill Flynn

SKILLS

C/C++ | Perl | Python | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Vincent Trudel-Lapierre

SKILLS

C/C++ | Matlab | Octave | Python | Scilab | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | Miscellaneous: Cryptography | Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Test Equipment |

Karim Abdel Hamid

SKILLS

C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Menaka Sajjan

SKILLS

Cadence Encounter | Cadence Virtuoso | Perl | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: ESD |

Shilpa Prabhu

VLSI Design Engineer

SKILLS

Cadence Encounter | Cadence Virtuoso | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Emre Goncu

SKILLS

Cadence Encounter | Cadence Virtuoso | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Vishal Prafulkumar Katigar

Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)

SKILLS

C/C++ | Perl | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers | Circuits: Sensors | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: PCB |

Ievgenii Meshcheriakov

SKILLS

C/C++ | Cadence Virtuoso | Python | Software Developer | VHDL |

AREA OF EXPERTISE

Analog: Design | System: PCB |

Pablo Cayuela

SKILLS

C/C++ | Electric CAD | Matlab | Octave | Scilab | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Digital: RTL | System: FPGA Programming |

Santhosh

IP & SoC Verification Engineer

SKILLS

Perl | System Verilog | Verilog | VHDL | UVM |

AREA OF EXPERTISE

Digital: Verification | SoC: Verification |

Hervé Pierre

Research engineer and teaching assistant in microelectronic, microsystems and bioelectronic at the university of Liège, Belgium

SKILLS

C/C++ | Electric CAD | Matlab | Python | Software Developer | SPICE Opus | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Circuits: Microcontrollers | Circuits: Sensors | Miscellaneous: Cryptography | System: FPGA Programming | System: PCB |

khaled

SKILLS

C/C++ | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

System: FPGA Programming |

Christopher Brian Young

SKILLS

C/C++ | Eagle CAD | Electric CAD | Hercules | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student |

Semiu A. Olowogemo

SKILLS

C/C++ | Cadence Virtuoso | Perl | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Mohamed Salem Abdelgalil

SKILLS

Perl | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | System: FPGA Programming |

Manoj S

Tech Lead

SKILLS

C/C++ | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | System: FPGA Programming |

harikrishna

Physical Design Engineer

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Rifat Demircioglu

Managing Partner

SKILLS

C/C++ | Leadership | Matlab | Perl | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Business: Design Services | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Ankit Adesara

SKILLS

Cadence Virtuoso | Eldo | Magic CAD | Matlab | Perl | Scilab | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Memory | System: FPGA Programming |

Syed Asad Alam

Post-doctoral research fellow in the discipline of Software and Systems, School of Computer Science and Statistics, Trinity College Dublin, with a keen interest in learning new things, specially related to computer science and engineering. Around 4 years experience of teaching and research and more than 10 years of experience in architecture design, optimization, analysis, implementation and verification of digital and digital signal processing systems on FPGAs and ASICs. Diversifying research career by working on quantization of deep convolution neural networks. Author of three peer reviewed journal publications and five international conference publications.

SKILLS

C/C++ | Matlab | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | System: FPGA Programming |

Alcides Silveira Costa

SKILLS

C/C++ | Leadership | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | CAD: Scripting | CAD: Tool Development | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Shyam K

SKILLS

Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Gordon Aplin

IC Design Engineer

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Magic CAD | ngspice | Perl | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

J. Rodriguez

Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.

SKILLS

C/C++ | System Verilog | System-C | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Bertrand PIGEARD

Hello, I'm an IC Designer Analog/RF with digital skills. I worked mainly on PLL for mobile tranceivers. I used to work on Cadence Design flow for 20 years.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Diva | Matlab | ngspice | Octave | Perl | Python | Scilab | SKILL | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Communication | Circuits: Memory | SoC: Floorplanning |

Ganesh Prasad B K

I am an electronics engineer currently working as an intern in STMicroelectronics.

SKILLS

Cadence Virtuoso | Calibre | Eldo | Matlab | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Simulation |

Mohammed Zakir Hussain

SKILLS

Cadence Encounter | Cadence Virtuoso | Magic CAD | Netgen | ngspice | Spectre | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Teaching | Digital: RTL | Digital: Synthesis |

Stephan Doucet

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Diva | Python | SKILL | Spectre | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Circuits: Communication |

RASHMI

Physical Design Engineer

SKILLS

C/C++ | Calibre | Matlab | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Dejan Mirkovic

Electronics Engineer and Researcher with a demonstrated history of working in the higher education industry. Skilled in CAD/EDA tools for ASIC, PCB and FPGA design, scripting and programming. Education professional with a PhD in Electrical Engineering and Computer Science from University of Nis, Faculty of Electronic Engineering Nis, Serbia.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Matlab | Octave | Python | SKILL | Spectre | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | CAD: Scripting | Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB |

Irfan Awan

SKILLS

VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers |

Ahmed Ramzy

SKILLS

C/C++ | Octave | System Verilog | Tanner L-Edit | Verilog | VHDL | ICC | DC |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

MADAN S

Analog circuit designer with passion in taking challenges .Interest in ADC,DAC,PLL,SDADC,LDO.Done layout of all these blocks.

SKILLS

Cadence Virtuoso | Calibre | Matlab | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation |

Luc Wong

I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Khaled Zaki Ahmed Hussein

MSC in Electrical Engineering BSC in Electronics Two patents in mathematical software in Engineering design and digital signal processing utility box Undergo private research for commercial use in the areas of very high frequency analog and digital circuits

SKILLS

C/C++ | Software Developer | VHDL | analog and mixed signal circuits design | digital circuits design |

AREA OF EXPERTISE

Analog: Design | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: DFT |

Vincent Pinon

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Octave | Perl | Python | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | Circuits: Communication | Circuits: Power Management | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | System: Test Programming |

Vrajesh Mistry

SKILLS

Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

System: FPGA Programming |

jatindersingh

SKILLS

Analog/Digital Circuit Design | C/C++ | Electric CAD | Magic CAD | ngspice | Python | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog-SMPS | Analog: Simulation | Analog: Verification | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital-DV | Digital-RTL | Digital: DFT | Digital: Placement and Routing | Miscellaneous: Neural Networks | SOC-DV | SoC: ESD | SoC: Floorplanning | SoC: Verification | System-DSP | System: Chip Editing | System: FPGA Programming |

Ankita Tiwari

Research Scholar

SKILLS

C/C++ | Leadership | ngspice | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Circuits: Memory | Miscellaneous: Neural Networks | System: FPGA Programming |

KADAR A A

I am researcher with goals of developing high end technologies for the future.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Leadership | Matlab | ngspice | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Digital: RTL | System: FPGA Programming |

Hesham Omran

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Eldo | Leadership | Matlab | Spectre | Tanner L-Edit | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Circuits: Sensors | Circuits: Signal Processing |

Edab

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Perl | Python | Software Developer | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | CAD: Scripting | Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Miscellaneous: Neural Networks | System: FPGA Programming |

Juanjo Garrido Serrato

SKILLS

VHDL | C | C++ | matlab |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Laurent Lamesch

HW development engineer

SKILLS

C/C++ | Eagle CAD | Matlab | Octave | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Test Equipment |

Josep Maria Sánchez Chiva

Current working in my PhD at BarcelonaTech.

SKILLS

Cadence Virtuoso | Calibre | Python | Spectre | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Sensors | SoC: Floorplanning | System: FPGA Programming | System: PCB |

Yuan Mei

An experimental physicist through sensor and instrumentation development.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Leadership | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Iago Sergio Pinheiro Pereira

SKILLS

C/C++ | Cadence Virtuoso | Electric CAD | Matlab | Octave | Python | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Simulation | Circuits: Signal Processing |

Marco Adel

SKILLS

Cadence Virtuoso | Calibre | Leadership | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout |

Mathieu Coustans

SKILLS

Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Spectre | System Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design |

Mahmoud Gamal Deghadi

.

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Eldo | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student |

Fabien Marteau

FPGA expert, interested by opensource tools for FPGA and for ASIC

SKILLS

Python | Verilog | VHDL |

AREA OF EXPERTISE

Business: Design Services |

Brian Glod

SKILLS

C/C++ | Eagle CAD | Python | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Martin Baudino

I am an Electronics Engineer with experience in IT Management, Firmware Development and Education. I spend my spare time looking for interesting projects and reading about technology trends.

SKILLS

C/C++ | Leadership | Matlab | Python | Software Developer | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Business: Management | Circuits: Microcontrollers | System: Test Equipment |

Mohammed Nabeel

Learner for life

SKILLS

Perl | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | System: FPGA Programming |

Mahmoud Youssuf Ahmad

Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: FPGA Programming |

Pedro Zamuner

SKILLS

C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | VHDL |

AREA OF EXPERTISE

CAD: Tool Development |

Marco Merlin

Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Octave | Python | SKILL | System Verilog | Verilog | VHDL | wifi | bluetooth | LTE |

AREA OF EXPERTISE

Analog: Verification | Circuits: Communication | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Neural Networks | SoC: Verification | System: PCB | System: Test Equipment | System: Test Programming |

Jose T. de Sousa

José T. de Sousa holds a PhD degree from Imperial College London (1998) and has been a university lecturer and researcher at Lisbon University (1999-present). He holds 4 international patents, is co-author of one book, and was General Chair of the Field Programmable Logic and Applications Conference in 2013. Dr. de Sousa has published more than 70 technical papers in international journals and conferences. He was co-founder and CEO of Coreworks, a semiconductor intellectual property company, which he ran from 2001 to 2013. His specialties are digital circuit design, hardware/software architecture, technical team management and semiconductor IP marketing and sales.

SKILLS

C/C++ | Cadence Encounter | Leadership | Matlab | Octave | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Business: Design Services | Business: Management | Business: Marketing | Business: Packaging | Business: Patents | Business: Public Relations | Business: Sales | CAD: Scripting |

Caio Alonso da Costa

SKILLS

C/C++ | Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | Digital: Verification |

AGhani

Associate Professor (Electrical and Electronic Engineering) Implantable chip design Low power sensors

SKILLS

Cadence Encounter | Cadence Virtuoso | Leadership | Matlab | SPICE Opus | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Sensors | Digital: Placement and Routing | Digital: RTL | System: Chip Editing | System: FPGA Programming |

Niels Moseley

SKILLS

C/C++ | Cadence Encounter | DSP | Matlab | Python | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | System: FPGA Programming |

Leonel ACUNHA GUIMARAES

SKILLS

Cadence Virtuoso | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Layout | CAD: Tool Development | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: Test Programming |

Botond Sandor Kirei

SKILLS

C/C++ | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Circuits: Filters | Circuits: Signal Processing | Digital: RTL |

Ping-Liang

SKILLS

Cadence Virtuoso | Matlab | Perl | Python | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design |

Staf Verhaegen

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Python | SKILL | Software Developer | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Open Source | SRAM | Standard Cells | Lithography |

ardencaple

Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.

SKILLS

C/C++ | Leadership | Python | Verilog | VHDL | DC | PrimeTime |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: Fabrication Process | System: FPGA Programming | Digital audio | IoT | Soc | Mixed Signal |

nik2402

I am an electronic hobbyist who enjoys building different electronic circuits and systems.

SKILLS

Cadence Virtuoso | Eagle CAD | Electric CAD | Matlab | Spectre | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Circuits: Power Management | Circuits: Signal Processing | System: PCB | System: Test Equipment | System: Test Programming |

Mustafa Sami

SKILLS

Cadence Virtuoso | Calibre | Matlab | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Communication | Circuits: Filters | Circuits: Power Management |

Don Morgan

SKILLS

C/C++ | Python | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

System: FPGA Programming |

Paulo Roberto Bueno de Carvalho

Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: FPGA Programming | System: PCB |

Pascal Buchschacher

designing mixed-mode ASICs since 1986 :-)

SKILLS

Cadence Virtuoso | Leadership | Matlab | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | SoC: Verification |

Hasan Mohamed

SKILLS

C/C++ | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Digital: RTL | Digital: Synthesis | Miscellaneous: Neural Networks | System: FPGA Programming |

ِAhmed

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Matlab | Spectre | System Verilog | Tcl/Tk | Verilog | VHDL | vb |

AREA OF EXPERTISE

Academic: Research | CAD: Tool Development |

Daniel

I'm a PCB designer, wanting to learn new technologies like FPGA and ASIC. Designing my own chip is my dream.

SKILLS

VHDL |

AREA OF EXPERTISE

System: PCB |

Youstina Maher

SKILLS

System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

CAD: Scripting | Digital: Synthesis |

Martin Simlastik

digital ASIC designer with 10+ yrs experience

SKILLS

Electric CAD | Matlab | Perl | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

IC |

JBU IC Design Group 1

Students in Introduction to IC Design Course working on an Encryption design for a class project

SKILLS

Electric CAD | VHDL |

AREA OF EXPERTISE

Academic: Student |

Akram Selim

SKILLS

Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Salma Hasan

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Jacob J Bushlack

SKILLS

C/C++ | Electric CAD | Octave | VHDL |

AREA OF EXPERTISE

Academic: Student |

Wilian D. Padilha

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Software Developer | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Circuits: Communication | Circuits: Power Management |

Jose Maria Hinojo

SKILLS

Allegro | Altium | C/C++ | Cadence Assura | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Perl | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: Chip Editing |

Muhammad Saufy Rohmad

Public University Lecturer in Computer Engineering. Passion about Computer Design.

SKILLS

C/C++ | Perl | VHDL |

AREA OF EXPERTISE

Academic: Research | Circuits: Microcontrollers |

Aditya Gupta

SKILLS

Cadence Virtuoso | Matlab | Python | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers |

Ankit wahane

pursuing pg in vlsi system design from vnit

SKILLS

ngspice | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Francisco Brito Filho

Electronic Engineer with experience in RF/AMS IC Design and other electronics and telecommunications projects. Served in working groups and also as leader. Has also experience in entrepreneurship. PhD in Microelectronics. Currently Adjunct Professor at Federal University of Semi-Árid Region - UFERSA and Head of LIEB/LAMERF Research Labs where develop R&D projects in the areas of instrumentation, biomedical engineering, RF/MW circuits and microelectronics.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Leadership | Matlab | ngspice | Octave | Python | Spectre | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Sensors | Miscellaneous: Neural Networks | System: FPGA Programming | RF Circuits and Systems | RF IC Design | Microwaves |

Prem Kumar A

A Mixed signal designer aspirant

SKILLS

Cadence Virtuoso | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student |

Diego Alessandro Bravo Pacheco

SKILLS

VHDL |

AREA OF EXPERTISE

Academic: Student |

Tung Hoang

R&D Engineer

SKILLS

Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: Floorplanning |

P Santosh Kumar Patra

I am a final year Masters student of NIT Rourkela, I am interested in SoC designing using RISCV ISA

SKILLS

C/C++ | Matlab | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Pablo Mendoza Ponce

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Python | Spectre | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research |

Vivek Parmar

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | ngspice | Octave | Python | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Modeling | Analog: Simulation | Circuits: Memory | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Test Equipment |

Risto Pejasinovic

SKILLS

C/C++ | Eagle CAD | Electric CAD | ngspice | Python | Software Developer | System Verilog | System-C | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Gustavo Linhares

i'm an eletronic engineer there are studing to became an IP desing

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Circuits: Signal Processing | System: FPGA Programming |

Kyle Laferty

SKILLS

Cadence Virtuoso | Calibre | Matlab | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout |

CHDL Custom High-Speed Digital Logic

We are group of experienced engineers working in Front-End Digital Logic Design.

SKILLS

Verilog | VHDL | MIPI | C-PHY | D-PHY |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis |

Yashas L.R

Technical Blogger and a Research Assistant in the field of analog VLSI Design.

SKILLS

assura | Cadence Virtuoso | Calibre | Electric CAD | Matlab | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Communication | Circuits: Filters | Circuits: Signal Processing |

Daniel Holley

SKILLS

C/C++ | Software Developer | System Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers |

Aliaa Fouli

Digital Logic Designer

SKILLS

Python | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Greg Cook

SKILLS

Python | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

System: PCB |

steven cramp

SKILLS

C/C++ | Matlab | Verilog | VHDL | spice | orcad |

AREA OF EXPERTISE

Academic: Student |

Andrew Selasi Agbemenu

Lecturer at the Department of Computer Engineering, Kwame Nkrumah University of Science and Technology, KNUST. My primary interest is in analog and mixed-signal design.

SKILLS

Cadence Virtuoso | Calibre | Matlab | ngspice | Python | Spectre | VHDL |

AREA OF EXPERTISE

Academic: Teaching |

Dr. Arun Ashok

Analog/RF designer with more than 10 years experience.

SKILLS

Cadence Virtuoso | Calibre | Matlab | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Circuits: Communication | Circuits: Power Management |

Joseph Kiniry

Dad. Partner. Scientist. Activist. Maker. — He/His

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Leadership | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | Bluespec | Chisel | EDA R&D |

AREA OF EXPERTISE

Academic: Research | Business: Design Services | Business: Management | CAD: Tool Development | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: Quality Assurance | System: Test Programming | Miscellaneous: Formal Methods |

Pepijn de Vos

SKILLS

C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | Spectre | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Digital: RTL | Digital: Synthesis |

Madhu Siddalingaiah

Artificial Intelligence/Machine Learning • Big Data • Internet of Things • Product Development

SKILLS

Eagle CAD | Leadership | LTspice | Python | Software Developer | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Analog: Verification |

Pratika Tripathi

I am Pratika Tripathi. I am in my final year of Btech. I am very interested in physical designing of IC. I had even taken 3 courses of kunal ghosh sir on physical design, stay, and cts. I am doing my final year project in physical design.

SKILLS

veilog | vhdl | asic flow | physical design | sta | fpga | vlsi |

AREA OF EXPERTISE

Academic: Research | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: Fabrication Process | System: FPGA Programming | System: Packaging |

RAJESH M

SKILLS

C/C++ | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Dennis Restle

SKILLS

C/C++ | Python | Scilab | Software Developer | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | System: FPGA Programming | System: PCB |

Bhuwan Kaushik

SKILLS

C/C++ | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Akil M

Undergraduate Student at NIT-Trichy

SKILLS

Eagle CAD | Matlab | ngspice | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Steven Bibyk

Associate Professor in Electrical and Computer Engr. Dept. Teaching and Research in Microelectronics. Teaching interests are in both discrete and integrated electronics, both for undergraduate electronics labs and projects and graduate integrated circuit design, verification, prototype, and test.

SKILLS

Cadence Virtuoso | Electric CAD | Leadership | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research |

Candido Aramburu Mayoz

Electronics Engineer

SKILLS

Matlab | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Academic: Teaching |

Damien Bonneau

R&D Engineer, interest in synthesis and verification software for electronics and photonics hardware

SKILLS

Python | Software Developer | VHDL |

AREA OF EXPERTISE

Academic: Research | CAD: Scripting | CAD: Tool Development | System: FPGA Programming |

Ahmed El-Omla

SKILLS

C/C++ | Python | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

Miscellaneous: Cryptography |

Furkan Ciylan

SKILLS

C/C++ | Matlab | Python | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Business: Packaging | Business: Patents | Business: PCB Manufacture |

Jan Bělohoubek

SKILLS

C/C++ | Magic CAD | ngspice | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Digital: RTL | Digital: Synthesis | Digital: Verification |

Sergey Churayev

SKILLS

Cadence Encounter | Cadence Virtuoso | Electric CAD | Matlab | ngspice | Octave | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Circuits: Microcontrollers | Circuits: Sensors | Digital: RTL | Miscellaneous: Cryptography | System: FPGA Programming |

sampath vp

Semiconductor

SKILLS

Cadence Encounter | Leadership | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Shubham Roy

SKILLS

ngspice | Octave | VHDL | fpga |

AREA OF EXPERTISE

Academic: Student |

Akhil

SKILLS

C/C++ | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student |

Hene Stuchi Saud

SKILLS

C/C++ | Cadence Virtuoso | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Halid Altuner

SKILLS

Python | Software Developer | System-C | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing |

Timothy Linden

SKILLS

C/C++ | Matlab | Software Developer | VHDL |

AREA OF EXPERTISE

Digital: RTL | System: FPGA Programming |

Thomas Parry

Mixed-signal designer

SKILLS

Cadence Virtuoso | Calibre | Matlab | Netgen | ngspice | Python | Spectre | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Digital: RTL | Digital: Verification |

Mustafa Khairallah

I am a Ph.D. student at the School of Physical and Mathematical Sciences, NTU, Singapore. I co-designed the Romulus and Remus families of lightweight authenticated encryption modes with Tetsu Iwata, Kazuhiko Minematsu and Thomas Peyrin, which are the basis of three candidates for the NIST Lightweight Cryptography Competition. Previously, I got my BSc. in Electronics Engineering from Alexandria University, Egypt. My main research focus is the practical aspects of Symmetric Key Cryptography, which includes: Physical Security, Hardware Implementations, Practical Cryptanalysis and Primitive Design. Previous research projects also included the acceleration of Fully Homomorphic Encryption and Design and Verification of Digital Circuits.

SKILLS

C/C++ | Cadence Encounter | Matlab | Octave | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL | perl |

AREA OF EXPERTISE

Academic: Research | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification |

Ken Pettit

Digital Systems and Software Engineer (formerly in management VP and Director of engineering).

SKILLS

C/C++ | Leadership | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB |

Loester Franco Botelho

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification | System: PCB |

Eloi Ramon

SKILLS

Electric CAD | Magic CAD | VHDL |

AREA OF EXPERTISE

Academic: Research |

Muhammad Ibrahim

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | System-C | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Academic: Student |

Phillip Pearson

SKILLS

C/C++ | Python | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | System: FPGA Programming | System: PCB |

Afonso Roberto Plantes Neto

SKILLS

Cadence Encounter | Cadence Virtuoso | Octave | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Filters | Circuits: Signal Processing |

Abbas Vahedi

SKILLS

C/C++ | Electric CAD | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Layout | CAD: Tool Development | Circuits: Microcontrollers | Circuits: Sensors | System: FPGA Programming | System: PCB |

Russell Friesenhahn

Hardware developer with FPGA and previous small test ASIC experience.

SKILLS

C/C++ | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Tristan Gingold

SKILLS

C/C++ | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

CAD: Tool Development | System: FPGA Programming |

Anton Blanchard

SKILLS

C/C++ | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Tom Stan

SKILLS

Cadence Virtuoso | Electric CAD | ngspice | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Circuits: Microcontrollers | System: PCB | System: Power Integrity | System: Signal Integrity |

Laurent Rougé

SKILLS

C/C++ | Python | VHDL | ASIC | FPGA | SoC |

AREA OF EXPERTISE

CAD: Scripting | CAD: Tool Development | Circuits: Communication | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Krister Borge

Department engineer at the University of Oslo.

SKILLS

Matlab | ngspice | Python | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching |

Vijay Raghuwanshi

SKILLS

C/C++ | Eagle CAD | Electric CAD | Matlab | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Pavan Sai

I am a final year B.Tech undergrad from India highly passionate about digital system design.

SKILLS

C/C++ | Leadership | Matlab | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | System: FPGA Programming |

Numan Abdullah

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eagle CAD | Magic CAD | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Miscellaneous: Neural Networks | System: Signal Integrity |

Rodrigo Drummond Lima

SKILLS

C/C++ | Matlab | Octave | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Bill Patterson

SKILLS

C/C++ | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | Digital: Synthesis |

Anthony Kung

Hi, I'm an Electrical & Computer Engineering + Computer Science student at Oregon State University.

SKILLS

C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | System: FPGA Programming |

Sylvain Munaut

SKILLS

C/C++ | Eagle CAD | Python | Scilab | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | System: FPGA Programming | System: PCB |

Arya Reais-Parsi

PhD Student @ UC Berkeley, formerly SWE @ Google

SKILLS

C/C++ | Python | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Analog: Layout | CAD: Tool Development | Digital: Placement and Routing | Digital: Synthesis |

Daniel Limbrick

I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.

SKILLS

C/C++ | Cadence Encounter | Calibre | Magic CAD | Matlab | ngspice | Octave | Perl | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Circuits: Microcontrollers | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Ahmed Yiwere

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | ngspice | Perl | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Circuits: Microcontrollers | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification |

James Stine

Edward Joullian Endowed Chair in Engineering Oklahoma State University Department of Electrical and Computer Engineering VLSI Computer Architecture Research Group

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Magic CAD | Matlab | Netgen | ngspice | Octave | Perl | Python | SKILL | Spectre | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research |

Estevao Coelho Teixeira

I am a professor at Federal University of Juiz de Fora (UFJF). I'm interested on analog and mixed-signal integrated circuits, as well as analog and digital electronics and microprocessors.

SKILLS

Electric CAD | Matlab | Netgen | Tanner L-Edit | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Circuits: Filters | Circuits: Microcontrollers | Circuits: Sensors | System: PCB |

Furkan Sahin

Senior FPGA Design Engineer

SKILLS

C/C++ | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Circuits: Signal Processing | Digital: RTL |

profiles search for skills: VHDL

171 results

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE

SKILLS

AREA OF EXPERTISE