profiles search for skills: Tcl/Tk
114 results
Kranthi Kumar Pamarthi
I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.
SKILLS
Sai Srinivas TNS
SKILLS
- Magic CAD | ngspice | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Praneeth
SKILLS
- Cadence Encounter | Cadence Virtuoso | Hercules | Perl | Spectre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Salman Sheikh
Senior Design Engineer at NASA-Goddard., Greenbelt, MD
AREA OF EXPERTISE
Sebastien Riou
SKILLS
- C/C++ | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Sokat
SKILLS
- Cadence Encounter | Perl | Tcl/Tk |
AREA OF EXPERTISE
Mohammed Essam Abd El Samee Soliman
I works as junior physical design engineer and I have passion in VLSI field specially in digital IC design. I have experience in writing RTL, test benches and in PnR flow.
AREA OF EXPERTISE
CHINTADA.GAYATRI
Physical Design Engineer
SKILLS
- C/C++ | Calibre | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Jeffery W. Carr
SKILLS
- C/C++ | Perl | Software Developer | Tcl/Tk |
AREA OF EXPERTISE
Eduardo Augusto da Costa
Eduardo is an Electrical Engineer engaged in hardware development with a true passion for developing and enhancing
applications. While at university, he worked in a variety of projects, from VHDL in a SOC project, to a PCB for a power circuit, and even web interfaces for electronic devices network connected. He allies his technical background with great communication skills. He is used to and is passionate about working in diverse cultural environment as was his period as an international student in Japan. He also got a certification in in Digital Integrated Circuit Design and Project Flow with Cadence tools (IC Brazil Program). Currently he works at HT Micron, and is interested in positions related to chip design, hardware design, embedded software development and similar areas.
SKILLS
- C/C++ | Cadence Encounter | Eagle CAD | Matlab | Octave | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Vachan U Bharadwaj
A recent graduate student from Syracuse University major in Electrical Engineering with focus in VLSI Designs
SKILLS
- Cadence Encounter | Cadence Virtuoso | Eagle CAD | Perl | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Rohit Yadav
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Electric CAD | Magic CAD | Matlab | Netgen | ngspice | Octave | Python | Scilab | SKILL | Spectre | SPICE Opus | System Verilog | System-C | Tcl/Tk | Verilog |
Peter Atkinson
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Stephane Badel
Physical design engineer
SKILLS
AREA OF EXPERTISE
Gautam Navapara
AREA OF EXPERTISE
Per Magnus Østhus
AREA OF EXPERTISE
Vincent Trudel-Lapierre
AREA OF EXPERTISE
Amit Prakash Gonnagar
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Electric CAD | Magic CAD | ngspice | Perl | Spectre | System Verilog | Tcl/Tk | Verilog |
Utsav D H Bhatt
AREA OF EXPERTISE
Santunu Sarangi
An energetic semiconductor professional with varied experience in the field of research, teaching and IC design.
📌 More than 6 years of experience in analog and mixed signal IC design.
📌 3 years of mentoring experience in analog circuit and layout design.
📌 Been part of the 4 complete IC development project.
📌 Inventor and co-inventor of 2 patents (filed) in the field of high-speed data path communication.
📌 Published few research papers with more than 30 engineering citations.
📌 6 month experience as a lead role in standard cell library development in a leading semiconductor organisation.
📌 more than 4 years of teaching experience in under-graduate electronics engineering courses.
SKILLS
- Cadence Virtuoso | Calibre | ngspice | Spectre | Tanner L-Edit | Tcl/Tk |
AREA OF EXPERTISE
Mohamed Salem Abdelgalil
AREA OF EXPERTISE
Manoj S
Tech Lead
AREA OF EXPERTISE
harikrishna
Physical Design Engineer
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Mustafa Khan Patan
AREA OF EXPERTISE
Rifat Demircioglu
Managing Partner
SKILLS
- C/C++ | Leadership | Matlab | Perl | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Kevin Huynh
AREA OF EXPERTISE
Alcides Silveira Costa
AREA OF EXPERTISE
Fenil
SKILLS
AREA OF EXPERTISE
RAJA KUMAR MEHTA
Physical Design Engineer
SKILLS
- C/C++ | Calibre | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Bertrand PIGEARD
Hello, I'm an IC Designer Analog/RF with digital skills.
I worked mainly on PLL for mobile tranceivers.
I used to work on Cadence Design flow for 20 years.
SKILLS
AREA OF EXPERTISE
Chaitanya Parashar
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Ganesh Prasad B K
I am an electronics engineer currently working as an intern in STMicroelectronics.
AREA OF EXPERTISE
MUVVA LAKSHMANKUMAR
SKILLS
- C/C++ | Cadence Encounter | Perl | Tcl/Tk | Verilog |
AREA OF EXPERTISE
RASHMI
Physical Design Engineer
AREA OF EXPERTISE
Shahbaz Abbasi
Design engineer with combined R&D and industrial experience in developing analog/mixed signal ICs for applications including inductive position sensors and imager readouts. Proven abilities with widely used blocks including (but not limited to) filter, amplifier, ADC, DAC, voltage regulators, bandgap reference, ring/LC oscillator, comparator and custom digital logic circuitry. Experience with full tape-out flow including schematic design, analog/mixed-signal simulations, floor planning, layout, system-level verification and chip measurements. Strong familiarity with industry standard tools and instruments used for design, verification and testing such as Cadence, Synopsys, Mentor Graphics, and Keysight. Frontend digital hardware design (ASIC/FPGA) experience using Verilog HDL. Considerable exposure to ASIC backend flow (synthesis and PnR) using Synopsys Design Compiler and Cadence Innovus. Skilled with programming platforms such as MATLAB, C++, C#, Perl, UNIX Shell and VB. Strong education with Ph.D. and MSc. degrees in Electronics Engineering along with several peer-reviewed articles in IEEE journals.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Perl | Python | Scilab | Software Developer | Spectre | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Filters | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB | System: Test Equipment | System: Test Programming |
Dejan Mirkovic
Electronics Engineer and Researcher with a demonstrated history of working in the higher education industry. Skilled in CAD/EDA tools for ASIC, PCB and FPGA design, scripting and programming. Education professional with a PhD in Electrical Engineering and Computer Science from University of Nis, Faculty of Electronic Engineering Nis, Serbia.
SKILLS
AREA OF EXPERTISE
Sajal Goyal
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Igor Danilov
SKILLS
- Cadence Encounter | Cadence Virtuoso | Python | Spectre | System Verilog | Tcl/Tk |
AREA OF EXPERTISE
Luc Wong
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Jiabin.Lv
physical design engineer.
7 years experience of backend design.
SKILLS
- Cadence Encounter | Calibre | Perl | Tcl/Tk |
AREA OF EXPERTISE
raju sake
AREA OF EXPERTISE
Vrajesh Mistry
AREA OF EXPERTISE
jatindersingh
SKILLS
- Analog/Digital Circuit Design | C/C++ | Electric CAD | Magic CAD | ngspice | Python | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | VLSI/ASIC and SoC Development |
AREA OF EXPERTISE
- Analog-SMPS | Analog: Simulation | Analog: Verification | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital-DV | Digital-RTL | Digital: DFT | Digital: Placement and Routing | Miscellaneous: Neural Networks | SOC-DV | SoC: ESD | SoC: Floorplanning | SoC: Verification | System-DSP | System: Chip Editing | System: FPGA Programming |
Anton Balbekov
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Leadership | Netgen | Python | SKILL | Software Developer | Spectre | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: Power Integrity |
Ankita Tiwari
Research Scholar
AREA OF EXPERTISE
Kevin Chou
AREA OF EXPERTISE
Yuan Mei
An experimental physicist through sensor and instrumentation development.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Leadership | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Ashbir Aviat Fadila
Analog and Mixed Signals Engineering Students
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Brian Glod
AREA OF EXPERTISE
- Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Mahmoud Youssuf Ahmad
Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Nambi
AREA OF EXPERTISE
Jose T. de Sousa
José T. de Sousa holds a PhD degree from Imperial College London (1998) and has been a university lecturer and researcher at Lisbon University (1999-present). He holds 4 international patents, is co-author of one book, and was General Chair of the Field Programmable Logic and Applications Conference in 2013. Dr. de Sousa has published more than 70 technical papers in international journals and conferences. He was co-founder and CEO of Coreworks, a semiconductor intellectual property company, which he ran from 2001 to 2013. His specialties are digital circuit design, hardware/software architecture, technical team management and semiconductor IP marketing and sales.
SKILLS
- C/C++ | Cadence Encounter | Leadership | Matlab | Octave | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |
Amr AbdelHadi AbdelHamid
SKILLS
- Cadence Virtuoso | Eldo | Perl | Tcl/Tk |
AREA OF EXPERTISE
Alfonso Chacon-Rodriguez
Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design.
Fiction writer (National Literature Award for Novel, 2011, Costa Rica)
SKILLS
- Calibre | Eldo | Electric CAD | Matlab | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Pushkaraksha K M
Physical design engineer with strong expertise in CAD and low power methodologies
SKILLS
- Cadence Encounter | Python | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Mustafa Sami
AREA OF EXPERTISE
Bob Ledzius
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
SKILLS
- C/C++ | Leadership | Matlab | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Business: Design Services | Business: Management | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: PCB |
Ernesto Conde
Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | ngspice | Python | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Arun Kumar V
4+ years of VLSI Backend experience. Working as Physical Design Engineer. Expertise in Analog layouts, physical verification and Physical Design. Open to learn and explore other domains of VLSI design.
AREA OF EXPERTISE
ِAhmed
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Matlab | Spectre | System Verilog | Tcl/Tk | Verilog | VHDL | vb |
AREA OF EXPERTISE
Youstina Maher
SKILLS
- System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Mahmoud Abdelgawad
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
fabien andrade
Graduated with a Micro-electronics Master from Bordeaux university, France, I have now 18 years of experience.
Worked in France, England, Belgium and Brazil, within 5 companies.
Implemented physical design flows, recruited, trained and supervised trainees to experienced engineers, I have a vast experience in setting up complete flow (2 companies were startups), as well as signing off important design within NXP and CSR, all to successful first time right silicons.
Able to work in total independence as well as within a team, I consider myself as optimist, result focused, with attention to detail while keeping a good trade between time to market and risk taking.
SKILLS
AREA OF EXPERTISE
Martin Simlastik
digital ASIC designer with 10+ yrs experience
SKILLS
- Electric CAD | Matlab | Perl | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- IC |
sto
Principle Engineer at efabless corporation
SKILLS
- C/C++ | Cadence Virtuoso | Diva | Electric CAD | Magic CAD | Netgen | ngspice | Octave | Python | SKILL | Software Developer | Tcl/Tk |
AREA OF EXPERTISE
Jose Maria Hinojo
SKILLS
- Allegro | Altium | C/C++ | Cadence Assura | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Perl | Tcl/Tk | VHDL |
AREA OF EXPERTISE
Thiago Coura
SKILLS
- Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Tigran Poghosyan
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Hercules | Python | Tcl/Tk |
AREA OF EXPERTISE
Siddhant Gandhi
SKILLS
AREA OF EXPERTISE
Santhosh Reddy
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Venkata Anurag N/A Atmakuri
I’m an engineer always looking to learn, optimize and automate.
I work on data analytics to provide deep insights into hardware designs, particularly physical design flow. Exploring areas to facilitate design engineers in taking data driven decisions for faster design turnaround times.
I like to think about life. I like experimenting with different techniques (using software tools and meditation) to optimize my day and work effectively. In my free time, I’m learning Web Programming to build my own blog. I know there are templates and websites but where’s the fun and learning if you don’t do it from scratch?
I like mentoring students on how to approach career and life in general.
SKILLS
- Python | System Verilog | Tcl/Tk | Cadence |
AREA OF EXPERTISE
Karan Kumar
SKILLS
- Cadence Virtuoso | Spectre | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Ricardo Godinez
AREA OF EXPERTISE
Maligi Sudharani
AREA OF EXPERTISE
Pablo Mendoza Ponce
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Python | Spectre | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Vivek Parmar
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | ngspice | Octave | Python | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |
Yaswanth Kumar Cherivirala
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | Spectre | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Vernon Greer
Analog IC Design Engineer with considerable expertise in mid- to high-frequency transistor-level design in the semiconductor industry, including clock synthesis, radio frequency circuitry (RF), and memory circuitry design. Experience also includes testing at board- and wafer-level, test automation, and simulation scripting.
SKILLS
AREA OF EXPERTISE
Geethanand N
Ex intel professional with over 5 years of experience in front end Vlsi
SKILLS
- Perl | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Nickson P Jose
SKILLS
- ASIC | Physical Design | STA | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Joseph Kiniry
Dad. Partner. Scientist. Activist. Maker. — He/His
SKILLS
- C/C++ | Cadence Virtuoso | Eagle CAD | Leadership | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | Bluespec | Chisel | EDA R&D |
AREA OF EXPERTISE
- Academic: Research | Business: Design Services | Business: Management | CAD: Tool Development | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: Quality Assurance | System: Test Programming | Miscellaneous: Formal Methods |
Allen Pan
SKILLS
- C/C++ | Software Developer | Tcl/Tk |
AREA OF EXPERTISE
Stefano
SKILLS
- C/C++ | Matlab | System Verilog | Tcl/Tk |
AREA OF EXPERTISE
Keerthan Nayak
AREA OF EXPERTISE
Suvrat Mishra
SKILLS
- System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Tanya Sharma
AREA OF EXPERTISE
Marc Rose
For most of my career, I was a CAD technology innovator and CAD system architect at Intel Corporation. I signed up recently for a Udemy class called "VSD - Making the Raven Chip: How to Design a RISC-V SoC." The class pointed me to Efabless.
SKILLS
- Perl | Software Developer | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Bhuwan Kaushik
AREA OF EXPERTISE
Candido Aramburu Mayoz
Electronics Engineer
AREA OF EXPERTISE
Furkan Ciylan
AREA OF EXPERTISE
ADITYA ANAND
SKILLS
- Cadence Encounter | Matlab | ngspice | Python | System Verilog | Tcl/Tk | Verilog |
sampath vp
Semiconductor
SKILLS
- Cadence Encounter | Leadership | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Hene Stuchi Saud
AREA OF EXPERTISE
Manish Mahajan
I am a design / verification Engineer for ASIC and FPGA .
SKILLS
- C/C++ | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Mustafa Khairallah
I am a Ph.D. student at the School of Physical and Mathematical Sciences, NTU, Singapore. I co-designed the Romulus and Remus families of lightweight authenticated encryption modes with Tetsu Iwata, Kazuhiko Minematsu and Thomas Peyrin, which are the basis of three candidates for the NIST Lightweight Cryptography Competition. Previously, I got my BSc. in Electronics Engineering from Alexandria University, Egypt. My main research focus is the practical aspects of Symmetric Key Cryptography, which includes: Physical Security, Hardware Implementations, Practical Cryptanalysis and Primitive Design. Previous research projects also included the acceleration of Fully Homomorphic Encryption and Design and Verification of Digital Circuits.
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL | perl |
AREA OF EXPERTISE
Soumil Krishnanand Heble
AREA OF EXPERTISE
Philipp Gühring
SKILLS
- C/C++ | Circuit Design | Magic CAD | ngspice | Perl | Python | Software Developer | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Tayyeb Mahmood
SKILLS
AREA OF EXPERTISE
Muhammad Ibrahim
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | System Verilog | System-C | Tcl/Tk | VHDL |
AREA OF EXPERTISE
Vipul Lengade
A curious VLSI engineer
AREA OF EXPERTISE
Afonso Roberto Plantes Neto
SKILLS
- Cadence Encounter | Cadence Virtuoso | Octave | Python | Spectre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
John Martinuk
Graduate Teaching Assistant of Purdue University's SoCET Team
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Matlab | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Omer Tariq
SKILLS
- Cadence Encounter | Python | System Verilog | Tcl/Tk |
AREA OF EXPERTISE
Matthew Ballance
SKILLS
- C/C++ | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Daniel Limbrick
I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.
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AREA OF EXPERTISE
James Stine
Edward Joullian Endowed Chair in Engineering
Oklahoma State University
Department of Electrical and Computer Engineering
VLSI Computer Architecture Research Group
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AREA OF EXPERTISE
