Tag results for: skills

Kranthi Kumar Pamarthi

I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.

SKILLS

Magic CAD | Matlab | Netgen | ngspice | Octave | Python | System Verilog | Tcl/Tk | Verilog | VHDL | perl |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Circuits: Filters | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | System: FPGA Programming |

Watson Huang

SKILLS

C/C++ | Python | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-RTL |

Juan Pablo Mena

SKILLS

C/C++ | Matlab | Python | Verilog |

AREA OF EXPERTISE

Digital-RTL |

Vishwajeet S B

I'm VLSI Design Engineer aspirant and like to work on design challenges in VLSI domain. I like to keep updated of cutting-edge technology in my field of interest.

SKILLS

Analog CMOS Circuit | Circuit Design | Matlab | Python | Verilog |

AREA OF EXPERTISE

Digital-RTL |

Aravind

I am a Application Engineer working for Cadence Design Systems and I facilitate the use of the Palladium Emulator at different Customers.

SKILLS

C/C++ | Perl | Python | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification | Design Automation |

Daniel J Wisehart

More than 25 years in FPGA design

SKILLS

C/C++ | Perl | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | SoC: Floorplanning | System: FPGA Programming |

Saravanan Nanthakumar

I am a Master Degree holder in VLSI Design. I am interested in Analog Circuit Design.

SKILLS

C/C++ | Electric CAD | Magic CAD | Matlab | ngspice | Octave | Python | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching |

Lefteris Kampianakis

SKILLS

Cadence Virtuoso | Eagle CAD | Matlab | Python | Software Developer | Spectre | VHDL | C | Java |

AREA OF EXPERTISE

Academic: Research | System: PCB |

Sahand Noorizadeh

SKILLS

Matlab | Python | RF | Analog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Filters | System: Packaging | System: PCB | System: Signal Integrity | System: Test Equipment |

Davy Huang

SKILLS

C/C++ | Circuit Design | Perl | Python | System-C | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | System-PCB | Digital-RTL |

Milan Kubavat

SKILLS

Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification |

Kullawat Chaowanawatee

SKILLS

C/C++ | Eagle CAD | Electric CAD | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Teaching | System: FPGA Programming | System: PCB |

Tim Edwards

Developer of open source EDA tools on Open Circuit Design

SKILLS

Analog CMOS Circuit | Analog IC Design | Analog/Digital Circuit Design | C/C++ | Circuit Design | Matlab | Python | Software Developer | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog | Analog IC | Analog IC Design | Analog-Layout | Analog-Mixed Signal-DV | Analog-Simulation | Analog-Verification | ASIC Design/Verification | Automatic Circuit Design | CAD-Dev | CAD-Scripts | Communication and Signal Processing | Cryptography | Design Automation | Digital-DFT | Evolutionary algorithm | signal processing | SOC-DV | SOC-ESD | SOC-Packaging | System-PCB | System-Signal-Integrity | Analog-ADC | Analog-LDO | Digital-BE | Digital-DV | Digital-RTL | System-DSP | System-Filters |

Samuel dos Santos Delgado

SKILLS

C/C++ | Magic CAD | Octave | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Circuits: Signal Processing | System: FPGA Programming | System: PCB |

Salman Sheikh

Senior Design Engineer at NASA-Goddard., Greenbelt, MD

SKILLS

Eagle CAD | Python | Software Developer | Tcl/Tk | Verilog | VHDL | C |

AREA OF EXPERTISE

System: FPGA Programming |

Sebastien Riou

SKILLS

C/C++ | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | Miscellaneous: Cryptography |

Deep Kalola

Physical Design Engineer, 5 Years of experience and always fascinate about learning new concepts. Open to understand & take participate in Open Source.

SKILLS

C/C++ | Circuit Design | Python | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | CAD-Scripts | System-Signal-Integrity |

Shubham Sarkar

SKILLS

Analog/Digital Circuit Design | C/C++ | Circuit Design | Python | Verilog |

AREA OF EXPERTISE

Digital-RTL |

Christian Lee Prather

Computer Science and Mechanical Engineering student

SKILLS

C/C++ | Eagle CAD | Matlab | Python |

AREA OF EXPERTISE

Academic: Student |

Rohit Yadav

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Electric CAD | Magic CAD | Matlab | Netgen | ngspice | Octave | Python | Scilab | SKILL | Spectre | SPICE Opus | System Verilog | System-C | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing |

Chris Burgess

Hobbyist maker interested in general electronics, with experience designing and fabricating custom circuit boards. https://tindie.com/stores/cburgess129

SKILLS

C/C++ | Eagle CAD | Python |

AREA OF EXPERTISE

Business: PCB Manufacture | Circuits: Microcontrollers | Circuits: Sensors | System: PCB |

Alberto Gomez

Passionate about Open Source RF Design!

SKILLS

Analog IC Design | C/C++ | Matlab | Python | Scilab |

AREA OF EXPERTISE

Analog-ADC | CAD-Scripts | SOC-ESD |

Peter Atkinson

SKILLS

C/C++ | Cadence Encounter | Matlab | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Prashant Dabholkar

FPGA Design Engineer

SKILLS

Analog/Digital Circuit Design | Python | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-RTL |

Kenneth Jose Rojas Rodriguez

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Python | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Circuits: Communication | System: PCB |

Mishel Paul

SKILLS

Python |

AREA OF EXPERTISE

CAD: Tool Development |

Ganesh V

ECE undergraduate looking to gain expertise in Analog/digital design.

SKILLS

Cadence Virtuoso | Python | SKILL | Software Developer | Spectre | Verilog |

AREA OF EXPERTISE

CAD: Scripting | Digital: Verification |

Ronan BARZIC

Principal Engineer at ONiO AS

SKILLS

C/C++ | Magic CAD | ngspice | Python | System-C | Verilog |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Power Management | Digital: RTL | Digital: Verification | Miscellaneous: Neural Networks | SoC: Verification |

Alexey Shabalovskiy

Expert in embedded and mobile applications since 2003. Has many years of experience in software and hardware development, effective team management. Excellent in the research and development, technology findings and implementations.

SKILLS

C/C++ | Leadership | Perl | Python | Software Developer | System-C |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Business: Design Services | Business: Management | CAD: Scripting | CAD: Tool Development | Circuits: Communication | Circuits: Microcontrollers | Digital: RTL | System: PCB | System: Quality Assurance | System: Test Programming |

Kenji Aono

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Python | Spectre |

AREA OF EXPERTISE

Academic: Research |

Per Magnus Østhus

SKILLS

C/C++ | Perl | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis |

Stephan Ahles

SKILLS

C/C++ | Cadence Virtuoso | Eldo | Electric CAD | Leadership | Matlab | ngspice | Octave | Python | SKILL | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Marketing | Business: Sales | CAD: Scripting | Circuits: Communication | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis |

Bill Flynn

SKILLS

C/C++ | Perl | Python | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Akhil Varghese Mathew

SKILLS

Cadence Virtuoso | Calibre | Matlab | Python | Spectre |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification |

Vincent Trudel-Lapierre

SKILLS

C/C++ | Matlab | Octave | Python | Scilab | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | Miscellaneous: Cryptography | Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Test Equipment |

Karim Abdel Hamid

SKILLS

C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Ben Marshall

SKILLS

C/C++ | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Circuits: Microcontrollers | Digital: RTL | Digital: Verification | Miscellaneous: Cryptography |

Pablo Sonna

SKILLS

C/C++ | Cadence Virtuoso | Python |

AREA OF EXPERTISE

Academic: Teaching | Analog: Design |

Marco Antonio Chang Kee Anselmo

SKILLS

Cadence Virtuoso | Python | SPICE Opus | Tanner L-Edit |

AREA OF EXPERTISE

Academic: Teaching |

Rohin Kumar Yeluripati

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Octave | Perl | Python |

AREA OF EXPERTISE

Academic: Research | Circuits: Microcontrollers | Miscellaneous: Neural Networks | System: PCB |

Jonathan Tremesaygues

SKILLS

Python |

AREA OF EXPERTISE

System: FPGA Programming |

Rafael Lima

SKILLS

C/C++ | Matlab | Python | Software Developer |

AREA OF EXPERTISE

Academic: Research | System: Test Programming |

Marwan Mohamed

I am a senior Electronics and Communications Engineering student at the Faculty of Engineering, Ain Shams University, Cairo, Egypt. I have wide knowledge and some experience in analog electronics with huge passion towards it

SKILLS

Cadence Virtuoso | Matlab | ngspice | Python |

AREA OF EXPERTISE

Academic: Student |

Jens Pejtersen

SKILLS

Cadence Virtuoso | Calibre | Matlab | Python | SKILL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification |

Ievgenii Meshcheriakov

SKILLS

C/C++ | Cadence Virtuoso | Python | Software Developer | VHDL |

AREA OF EXPERTISE

Analog: Design | System: PCB |

Tim 'mithro' Ansell

SKILLS

C/C++ | Python |

AREA OF EXPERTISE

Soft |

Bernd Waschneck

www.waschneck.com

SKILLS

C/C++ | Circuit Design | Python |

AREA OF EXPERTISE

Automatic Circuit Design | Cryptography | Evolutionary algorithm |

Hervé Pierre

Research engineer and teaching assistant in microelectronic, microsystems and bioelectronic at the university of Liège, Belgium

SKILLS

C/C++ | Electric CAD | Matlab | Python | Software Developer | SPICE Opus | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Circuits: Microcontrollers | Circuits: Sensors | Miscellaneous: Cryptography | System: FPGA Programming | System: PCB |

Saroj Rout

Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.

SKILLS

Calibre | Eagle CAD | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Scilab | SKILL | Spectre | System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | CAD: Scripting | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | SoC: ESD | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Semiu A. Olowogemo

SKILLS

C/C++ | Cadence Virtuoso | Perl | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Eamonn Lieske

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | ngspice | Octave | Python |

AREA OF EXPERTISE

Academic: Research | Analog: Design | CAD: Tool Development | Circuits: Communication | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing |

Rejoy Roy Mathews

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Digital: RTL |

Amudhan Balasubramanian

Over 25+ years of experience Silicon Engineer with focus on taking a Silicon from GDS2 to PRQ. Involved in Wafersort testing, Packaging, Packaging Testing, Silicon Characterisation - Electrical & Functional, Package Qualification, Reliablity testing and Yield management

SKILLS

Leadership | Python | Verilog |

AREA OF EXPERTISE

Business: Foundry Services | Business: Management | Business: Packaging | Business: PCB Manufacture | System: Fabrication Process | System: Packaging | System: PCB | System: Quality Assurance | System: Test Equipment | System: Test Programming |

Syed Asad Alam

Post-doctoral research fellow in the discipline of Software and Systems, School of Computer Science and Statistics, Trinity College Dublin, with a keen interest in learning new things, specially related to computer science and engineering. Around 4 years experience of teaching and research and more than 10 years of experience in architecture design, optimization, analysis, implementation and verification of digital and digital signal processing systems on FPGAs and ASICs. Diversifying research career by working on quantization of deep convolution neural networks. Author of three peer reviewed journal publications and five international conference publications.

SKILLS

C/C++ | Matlab | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | System: FPGA Programming |

Kevin Huynh

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Perl | Python | Scilab | Spectre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Circuits: Communication | Circuits: Filters |

Alcides Silveira Costa

SKILLS

C/C++ | Leadership | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | CAD: Scripting | CAD: Tool Development | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Sumanta

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | Digital: Verification | System: FPGA Programming |

Judd Jenne

SKILLS

C/C++ | Calibre | Python | Software Developer | System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | System: FPGA Programming |

Bertrand PIGEARD

Hello, I'm an IC Designer Analog/RF with digital skills. I worked mainly on PLL for mobile tranceivers. I used to work on Cadence Design flow for 20 years.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Diva | Matlab | ngspice | Octave | Perl | Python | Scilab | SKILL | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Communication | Circuits: Memory | SoC: Floorplanning |

Mohammad Malik

SKILLS

Python |

AREA OF EXPERTISE

Academic: Research |

M Aznan Firmansyah B

real engineer

SKILLS

Analog IC Design | C/C++ | Circuit Design | Matlab | Python | Scilab | Software Developer |

AREA OF EXPERTISE

Design Automation | Industrial Engineering |

Mustafa Tosun

I am a digital design/verification engineer. I have 2 years of full-time industry experience. In total, I have 4.5 years of experience in RTL design, Electronic Design Automation and Verification using VHDL/Verilog, Perl, Tcl and Linux. I was the #1 graduate of Bahcesehir University in Mechatronics Engineering in 2013

SKILLS

C/C++ | Matlab | Perl | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Communication and Signal Processing | Design Automation | Digital-RTL |

Will Burke

Hardware Engineer

SKILLS

Circuit Design | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Automatic Circuit Design | Digital-BE | Digital-RTL |

Ganesh Prasad B K

I am an electronics engineer currently working as an intern in STMicroelectronics.

SKILLS

Cadence Virtuoso | Calibre | Eldo | Matlab | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Simulation |

Stephan Doucet

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Diva | Python | SKILL | Spectre | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Circuits: Communication |

Muthukumar

SKILLS

Cadence Virtuoso | Calibre | Eldo | Python | Spectre | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Digital: Placement and Routing | Digital: Synthesis | System: FPGA Programming |

Alfonso Breglia

SKILLS

Analog IC Design | Analog/Digital Circuit Design | C/C++ | Circuit Design | Matlab | Python | Software Developer |

AREA OF EXPERTISE

Analog | Analog-Amplifiers | Analog-Modeling | Analog-Simulation | Digital-DFT | Evolutionary algorithm | Industrial Engineering |

Ashutosh Jain

SKILLS

Analog/Digital Circuit Design | Matlab | Python | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-RTL |

Shahbaz Abbasi

Design engineer with combined R&D and industrial experience in developing analog/mixed signal ICs for applications including inductive position sensors and imager readouts. Proven abilities with widely used blocks including (but not limited to) filter, amplifier, ADC, DAC, voltage regulators, bandgap reference, ring/LC oscillator, comparator and custom digital logic circuitry. Experience with full tape-out flow including schematic design, analog/mixed-signal simulations, floor planning, layout, system-level verification and chip measurements. Strong familiarity with industry standard tools and instruments used for design, verification and testing such as Cadence, Synopsys, Mentor Graphics, and Keysight. Frontend digital hardware design (ASIC/FPGA) experience using Verilog HDL. Considerable exposure to ASIC backend flow (synthesis and PnR) using Synopsys Design Compiler and Cadence Innovus. Skilled with programming platforms such as MATLAB, C++, C#, Perl, UNIX Shell and VB. Strong education with Ph.D. and MSc. degrees in Electronics Engineering along with several peer-reviewed articles in IEEE journals.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Perl | Python | Scilab | Software Developer | Spectre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Filters | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB | System: Test Equipment | System: Test Programming |

Zheng Lai

SKILLS

C/C++ | Cadence Virtuoso | Python | Software Developer | Spectre | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Analog: Verification | CAD: Tool Development | Circuits: Communication | Miscellaneous: Neural Networks | System: FPGA Programming |

Dejan Mirkovic

Electronics Engineer and Researcher with a demonstrated history of working in the higher education industry. Skilled in CAD/EDA tools for ASIC, PCB and FPGA design, scripting and programming. Education professional with a PhD in Electrical Engineering and Computer Science from University of Nis, Faculty of Electronic Engineering Nis, Serbia.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Matlab | Octave | Python | SKILL | Spectre | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | CAD: Scripting | Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB |

Pooja bilkar

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Synthesis | Digital: Verification |

Darshan Guled

hello, my name is Darshan Guled, i am an engineering student and i am working on PICO RISc processor and RAVEN chip,

SKILLS

C/C++ | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

ray chen

SKILLS

Cadence Virtuoso | Calibre | Python | Spectre |

AREA OF EXPERTISE

Analog: Design | Analog: Modeling | Circuits: Sensors |

Constantin Runge

SKILLS

C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | Software Developer | Spectre | Julia |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Simulation | Circuits: Filters | Circuits: Signal Processing | Digital: DFT | Miscellaneous: Neural Networks |

Guy Hutchison

ASIC Designer and entrepreneur

SKILLS

C/C++ | Leadership | Python | Verilog | chisel |

AREA OF EXPERTISE

Digital: RTL | Miscellaneous: Cryptography |

Mario Vigliar

Mad about OSS system design, specialized in video compression and image processing, CNN and dedicated HPC architectures. New deals in low power design

SKILLS

C/C++ | Circuit Design | Matlab | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-RTL | System-DSP | System-Filters |

Igor Danilov

SKILLS

Cadence Encounter | Cadence Virtuoso | Python | Spectre | System Verilog | Tcl/Tk |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | CAD: Scripting | Digital: RTL | Digital: Synthesis | Digital: Verification |

Luc Wong

I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |

raju sake

SKILLS

Python | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research |

Kaushik Parthasarathy

Electronics Engineer

SKILLS

Cadence Virtuoso | Electric CAD | Python | System Verilog |

AREA OF EXPERTISE

Analog: Design |

Baris Volkan Yildirim

Design engineer

SKILLS

Analog CMOS Circuit | Analog IC Design | Eldo | Matlab | Python | System Verilog |

AREA OF EXPERTISE

Academic: Research | Analog-Amplifiers | Analog: Design | Analog: Modeling | Analog: Verification | Business: Sales | Circuits: Filters | Circuits: Power Management |

Kousuke Nakamura

SKILLS

Electric CAD | Python | Tanner L-Edit |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification |

Vincent Pinon

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Octave | Perl | Python | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | Circuits: Communication | Circuits: Power Management | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | System: Test Programming |

Sanjay Mehta

30+ years of experience ranging across telecom, embedded systems, semiconductor, firmware development.

SKILLS

C/C++ | Python | Firmware | System Architecture | Embedded Systems | Telecom |

AREA OF EXPERTISE

Business: Design Services |

Shivani Shah

SKILLS

C/C++ | Matlab | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

jatindersingh

SKILLS

Analog/Digital Circuit Design | C/C++ | Electric CAD | Magic CAD | ngspice | Python | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog-SMPS | Analog: Simulation | Analog: Verification | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital-DV | Digital-RTL | Digital: DFT | Digital: Placement and Routing | Miscellaneous: Neural Networks | SOC-DV | SoC: ESD | SoC: Floorplanning | SoC: Verification | System-DSP | System: Chip Editing | System: FPGA Programming |

Michael OBrien

SKILLS

C/C++ | Matlab | Python |

AREA OF EXPERTISE

System: Test Programming |

Srimanth

SKILLS

Eagle CAD | Python | Software Developer | Verilog |

AREA OF EXPERTISE

SoC: Verification |

Pavan Kumar Pothula

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Debasis Sahu

SKILLS

Cadence Virtuoso | Calibre | Leadership | ngspice | Perl | Python | SKILL | Tanner L-Edit |

AREA OF EXPERTISE

Analog: Layout | Business: Management | Business: Marketing | CAD: Scripting |

James Tandon

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eagle CAD | Eldo | Leadership | Magic CAD | Matlab | Octave | Perl | Python | Scilab | Software Developer | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Business: Design Services | CAD: Tool Development | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: Chip Editing | System: FPGA Programming | System: PCB |

Anton Balbekov

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Leadership | Netgen | Python | SKILL | Software Developer | Spectre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: Power Integrity |

Ankita Tiwari

Research Scholar

SKILLS

C/C++ | Leadership | ngspice | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Circuits: Memory | Miscellaneous: Neural Networks | System: FPGA Programming |

patrick reynen

entrepreneur in IT & IoT

SKILLS

C/C++ | Circuit Design | Python | Software Developer |

AREA OF EXPERTISE

Design Automation | Industrial Engineering |

Jeff

I work at efabless

SKILLS

Python |

AREA OF EXPERTISE

Business: Management |

Hasith Ishara

Graduated 4 tears back in engineering specialized in electronics and telecommuniation engineering with a first class. Now I am working at a startup as the team lead of the embedded design team. I am also a postgraduate student in Msc in wireless communication engineering course. Creon Solutions is my freelancer name. I do image processing, PCB and circuit designs ...etc in Freelancer.com

SKILLS

C/C++ | Matlab | Python | Software Developer |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | System: PCB | System: Power Integrity | System: Signal Integrity |

Edab

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Perl | Python | Software Developer | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | CAD: Scripting | Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Miscellaneous: Neural Networks | System: FPGA Programming |

Mark Omo

I am an Electrical Engineer at Marcus Engineering working primarily on embedded systems in a wide range of applications in the Medical, Military and Aerospace sectors.

SKILLS

Analog CMOS Circuit | C/C++ | Eagle CAD | Python |

AREA OF EXPERTISE

Analog IC | Analog: Design |

Dave Cameron

SKILLS

C/C++ | Magic CAD | Python | Software Developer | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | System: PCB |

Kevin Chou

SKILLS

C/C++ | Eldo | Matlab | ngspice | Octave | Python | Software Developer | Spectre | Tcl/Tk |

AREA OF EXPERTISE

CAD: Tool Development |

Jean Carlos Schenuemann

SKILLS

C/C++ | Circuit Design | Matlab | Python | Software Developer | Verilog |

AREA OF EXPERTISE

signal processing | System-DSP | System-Filters |

Cayce Ullman

Serial Entrepreneur

SKILLS

C/C++ | Perl | Python | Software Developer |

AREA OF EXPERTISE

Cryptography | Security |

Vicente Amorim

SKILLS

C/C++ | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Teaching |

Shri Prakash

SKILLS

Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

SOC-DV | Digital-RTL |

Jose Joaquin Mendoza

SKILLS

C/C++ | Matlab | Python | Verilog |

AREA OF EXPERTISE

Communication and Signal Processing |

Hyunjin Noh

SKILLS

C/C++ | Matlab | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Design Automation | Digital-RTL |

Marcus N

System and database administrator, embedded systems hobbyist.

SKILLS

C/C++ | Perl | Python | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | System: FPGA Programming |

Andrew P. Lentvorski

SKILLS

Python |

AREA OF EXPERTISE

Circuits: Power Management |

Shabab Alam

SKILLS

Cadence Virtuoso | Magic CAD | Matlab | Netgen | Python |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Circuits: Memory | Digital: DFT |

Josep Maria Sánchez Chiva

Current working in my PhD at BarcelonaTech.

SKILLS

Cadence Virtuoso | Calibre | Python | Spectre | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Sensors | SoC: Floorplanning | System: FPGA Programming | System: PCB |

Nick Ford

SKILLS

Eagle CAD | Python | Orcad | Altium |

AREA OF EXPERTISE

System: PCB |

Yuan Mei

An experimental physicist through sensor and instrumentation development.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Leadership | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Joaquín Venegas

SKILLS

Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-RTL |

Ronobir Das

BSEE graduating senior with a focus in digital design. I have taken coursework in Analog, Digital, Mixed Signal and RF IC design, and have experience using Cadence's tool suite as well as NI's AWR. I have also done multiple EDA centric courses in validation, formal and functional verification and Digital IC Testing

SKILLS

Analog/Digital Circuit Design | C/C++ | Python | System-C | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification |

Iago Sergio Pinheiro Pereira

SKILLS

C/C++ | Cadence Virtuoso | Electric CAD | Matlab | Octave | Python | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Simulation | Circuits: Signal Processing |

Aleksandar Kostovic

Freelancer

SKILLS

Circuit Design | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog IC Design | ASIC Design/Verification | Automatic Circuit Design | System-PCB |

Brandon

SKILLS

C/C++ | Leadership | Python |

AREA OF EXPERTISE

Academic: Student |

Shams Tabrej

SKILLS

Python | Software Developer |

AREA OF EXPERTISE

Analog |

Gregory Davill

Full time: Electronics Engineer with an interest in embedded systems solutions. I can take a project goal and design, develop, prototype, program, validate an embedded system reaching that goal. Part-time: Maker, interested in rapid prototyping, my lab has basic machines: CO2 Laser cutter, 3d printers, small milling machine. I've built 3 of my own 3d printers.

SKILLS

Analog/Digital Circuit Design | C/C++ | Circuit Design | Matlab | Python | Software Developer |

AREA OF EXPERTISE

CAD-Dev | CAD-Scripts | Industrial Engineering | signal processing | System-PCB |

Michael Vacek

SKILLS

C/C++ | Circuit Design | Matlab | Python | Software Developer | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Communication and Signal Processing | signal processing | System-PCB | Digital-RTL | System-DSP |

Eric Hawkins

Manager of Universal Avionics System Corporation(UASC) PLD design group. This group is tasked with designing, implementing and approving, in accordance with RTCA/DO-254 guidance, all ASIC/FPGA used in the Universal Avionics product line.

SKILLS

Analog/Digital Circuit Design | Circuit Design | Perl | Python | Scilab | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification |

Jeff DiCorpo

I'm a staff member at efabless responsible for product management, business development, strategy, partnerships.

SKILLS

business developement | C/C++ | product development | product marketing | Python | Software Developer | strategic partnerships |

AREA OF EXPERTISE

AWS infrastructure | Design Automation |

Anton Paquin

EE student. ++ Neuromorphic circuits

SKILLS

Analog/Digital Circuit Design | Python | Verilog |

AREA OF EXPERTISE

CAD-Scripts | Digital-RTL |

Fabien Marteau

FPGA expert, interested by opensource tools for FPGA and for ASIC

SKILLS

Python | Verilog | VHDL |

AREA OF EXPERTISE

Business: Design Services |

Stepan Sutula

I received the B.S. degree in Industrial Electronics Engineering from the Universitat Politècnica de Catalunya, Spain, in 2007, and the M.S. degree in Micro- and Nanoelectronics Engineering in 2009 and the Ph.D. degree in Microelectronics and Electronic Systems in 2015 both from the Universitat Autònoma de Barcelona, Spain. From 2006 to 2008, I was with Investigation Total Ware, S.A., Spain, where I was engaged in analog and mixed-signal circuit design for highly reliable wireless telecommunication systems. From 2008 to 2015, I was with the Integrated Circuits and Systems design group at the Institut de Microelectrònica de Barcelona, CNM, CSIC, Spain, designing low-power high-precision mixed-signal ASICs for integrated smart sensors and IP blocks. From 2015 to 2016, I was with Broadcom Ltd., Barcelona, Spain, developing low-power CMOS IPs like low-temperature-drift oscillators, varible-temperature-coefficient current/voltage generators, temperature sensors, cross-domain level shifting and biasing circuits, touch-sensor transmitter drivers. I am co-author of 12 publications and participant in several research and industrial projects using a wide range of CMOS technology nodes. I am recipient of the 2007 Highest Grade Point Average in the Graduating Class Award, the 2014 Best Paper Award and the 2015 Student Best Paper Award Honorable Mention. My skills include: high-performance continuous-time/switched-capacitor circuits such as low-power high-resolution ADCs/DACs using Class-AB OpAmps; system high-level modeling (SciPy/Sage, Matlab); system electrical-level modeling (Verilog/-A/-AMS); EKV circuit-level modeling; full-custom IC design cycle (gEDA Tools/Cadence Virtuoso: from schematics to layout and verification); development of low-noise and low-distortion test equipment (including microcontrollers and FPGAs) and software (using C++, Tcl, VB, Python); and, experimental IC measures and parameter extraction.

SKILLS

Analog CMOS Circuit | Analog | Analog IC Design | Analog/Digital Circuit Design | C/C++ | Circuit Design | Matlab | Python | Software Developer | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog | Analog IC | Analog IC Design | Analog-Amplifiers | Analog-Layout | Analog-Mixed Signal-DV | Analog-Modeling | Analog-Simulation | Analog-Verification | ASIC Design/Verification | Automatic Circuit Design | CAD-Dev | CAD-Scripts | Communication and Signal Processing | Design Automation | Industrial Engineering | signal processing | SOC-DV | SOC-Packaging | System-PCB | System-Power-Integrity | System-Signal-Integrity | Analog-ADC | Analog-LDO | Digital-DV | System-Filters |

Valérian Lalucaa

SKILLS

Cadence Virtuoso | Matlab | Python |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Circuits: Sensors |

Vasyl Yosypenko

Embedded System Engineer

SKILLS

Analog/Digital Circuit Design | C/C++ | Python | Software Developer |

AREA OF EXPERTISE

Analog-Verification | Automatic Circuit Design | Design Automation | System-PCB | Analog-ADC |

Brian Glod

SKILLS

C/C++ | Eagle CAD | Python | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Sebastián Guerrero

SKILLS

Analog CMOS Circuit | Analog/Digital Circuit Design | Python | Verilog |

AREA OF EXPERTISE

Analog-Amplifiers | Analog-Mixed Signal-DV |

Martin Baudino

I am an Electronics Engineer with experience in IT Management, Firmware Development and Education. I spend my spare time looking for interesting projects and reading about technology trends.

SKILLS

C/C++ | Leadership | Matlab | Python | Software Developer | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Business: Management | Circuits: Microcontrollers | System: Test Equipment |

Mohammed Nabeel

Learner for life

SKILLS

Perl | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | System: FPGA Programming |

Sean Cross

SKILLS

C/C++ | Perl | Python | Verilog |

AREA OF EXPERTISE

Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Quality Assurance | System: Test Programming |

Federico Paredes

Digital designer experienced in high-speed ASICs for optical/copper transceivers, including DSPs, error correction and SoC support.

SKILLS

C/C++ | Cadence Encounter | Matlab | Octave | Python | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Communication | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Karan Shah

SKILLS

Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification |

Luis Enrique Rodriguez Mecca

Analog IC designer with knowledge and experience related to topics in analogl full-custom IC design such as current mirrors, single and differential amplifiers, bandgaps circuits and charge pump.

SKILLS

Analog CMOS Circuit | Analog IC Design | Matlab | Python | Verilog |

AREA OF EXPERTISE

Analog IC | Analog-Amplifiers | Analog-Layout |

Stephan Kanthak

SKILLS

C/C++ | ngspice | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Miscellaneous: Neural Networks |

Sheung Lu

Graduate student working on CMOS based biosensors.

SKILLS

Cadence Encounter | Cadence Virtuoso | Matlab | Python | Spectre |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Nambi

SKILLS

C/C++ | ngspice | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Verification | Business: Design Services | CAD: Tool Development | Digital: Verification | SoC: Verification |

Dan White

Valparaiso University - College of Engineering - ECE professor

SKILLS

Analog CMOS Circuit | Analog | Analog IC Design | Analog/Digital Circuit Design | C/C++ | Circuit Design | Python | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog IC Design | Analog-Amplifiers | Analog-Layout | Analog-Modeling | Communication and Signal Processing | System-Signal-Integrity | System-DSP |

Clifford Wolf

Author of Yosys, IceStorm, PicoRV32, and other Open Source things

SKILLS

C/C++ | Circuit Design | Python | Software Developer | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification | Automatic Circuit Design | CAD-Dev | CAD-Scripts | Design Automation | Digital-DV | Digital-RTL | Evolutionary algorithm | signal processing |

Pedro Zamuner

SKILLS

C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | VHDL |

AREA OF EXPERTISE

CAD: Tool Development |

Marco Merlin

Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Octave | Python | SKILL | System Verilog | Verilog | VHDL | wifi | bluetooth | LTE |

AREA OF EXPERTISE

Analog: Verification | Circuits: Communication | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Neural Networks | SoC: Verification | System: PCB | System: Test Equipment | System: Test Programming |

Rama Kotapally

I have 20 years of experience in Circuit Design, Physical Design, RTL.

SKILLS

Circuit Design | Perl | Python | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-BE | Digital-RTL |

Discoverer

Enthusiastic analog designer

SKILLS

Cadence Virtuoso | ngspice | Octave | Python | SKILL | Software Developer | Spectre |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | CAD: Scripting | Circuits: Power Management |

Vasilis Goulemes

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Python |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing |

Jose T. de Sousa

José T. de Sousa holds a PhD degree from Imperial College London (1998) and has been a university lecturer and researcher at Lisbon University (1999-present). He holds 4 international patents, is co-author of one book, and was General Chair of the Field Programmable Logic and Applications Conference in 2013. Dr. de Sousa has published more than 70 technical papers in international journals and conferences. He was co-founder and CEO of Coreworks, a semiconductor intellectual property company, which he ran from 2001 to 2013. His specialties are digital circuit design, hardware/software architecture, technical team management and semiconductor IP marketing and sales.

SKILLS

C/C++ | Cadence Encounter | Leadership | Matlab | Octave | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Business: Design Services | Business: Management | Business: Marketing | Business: Packaging | Business: Patents | Business: Public Relations | Business: Sales | CAD: Scripting |

Colin Hart

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | CAD: Tool Development | Circuits: Communication | System: PCB | System: Test Equipment |

David Ward

Circuit Designer

SKILLS

Analog CMOS Circuit | Analog | Analog IC Design | Analog/Digital Circuit Design | Circuit Design | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog | Analog IC | Analog IC Design | Analog-Amplifiers | Analog-Layout | Analog-Mixed Signal-DV | Analog-Modeling | Analog-Simulation | ASIC Design/Verification |

Niels Moseley

SKILLS

C/C++ | Cadence Encounter | DSP | Matlab | Python | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | System: FPGA Programming |

Camillo

Experienced Analog Design Engineer with strong background in HV CMOS ASICs.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Octave | Perl | Python | SKILL | Spectre |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Power Management | SoC: ESD | SoC: Floorplanning | System: PCB |

Cristian Hamanaka

Analog IC Designer

SKILLS

Cadence Virtuoso | Calibre | Eldo | Python |

AREA OF EXPERTISE

Academic: Research |

Shimon Hempling

SKILLS

Magic CAD | Python | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Ping-Liang

SKILLS

Cadence Virtuoso | Matlab | Perl | Python | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design |

Caspar van VRoonhoven

>10 years of experience in precision analog and sensor interface IC design.

SKILLS

C/C++ | Cadence Virtuoso | Leadership | Python | SKILL | Spectre | Verilog | Precision | Verilog-AMS | ADCs | Sensors | Reference circuits |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Sensors |

Staf Verhaegen

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Python | SKILL | Software Developer | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Open Source | SRAM | Standard Cells | Lithography |

Hajime Suzuki

SKILLS

Analog CMOS Circuit | Analog IC Design | Matlab | Python | Verilog |

AREA OF EXPERTISE

Analog IC Design |

Yao Ming Kuo

Hardware design engineer

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Alfonso Chacon-Rodriguez

Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design. Fiction writer (National Literature Award for Novel, 2011, Costa Rica)

SKILLS

Calibre | Eldo | Electric CAD | Matlab | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Raffaele Breglia

Electronic engineer

SKILLS

C/C++ | Python | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Industrial Engineering |

Pushkaraksha K M

Physical design engineer with strong expertise in CAD and low power methodologies

SKILLS

Cadence Encounter | Python | Tcl/Tk | Verilog |

AREA OF EXPERTISE

CAD: Tool Development | Digital: Placement and Routing | SoC: Floorplanning |

ardencaple

Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.

SKILLS

C/C++ | Leadership | Python | Verilog | VHDL | DC | PrimeTime |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: Fabrication Process | System: FPGA Programming | Digital audio | IoT | Soc | Mixed Signal |

Matthew Ernest

VLSI circuit design engineer with significant experience in microprocessor design in semiconductor processes from 65nm to 10nm. Provided register file designs and design training for Intel Big Core and SOC projects. Helped create semi-automated array layout methodology. Established cross-organizational methodology for variation analysis in register files. Converged memory IP handling across multiple organizations.

SKILLS

Analog/Digital Circuit Design | Circuit Design | Perl | Python | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Design Automation | Digital-BE | Digital-DV |

Jacob Rast

SKILLS

Analog/Digital Circuit Design | C/C++ | Matlab | Python | Verilog |

AREA OF EXPERTISE

Analog |

ahmed gendy

Analog Mixed design engineer

SKILLS

Analog/Digital Circuit Design | Circuit Design | Perl | Python |

AREA OF EXPERTISE

Analog-Mixed Signal-DV | Analog-Simulation |

ernesto

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Python | Spectre |

AREA OF EXPERTISE

Analog: Design | Circuits: Communication | Circuits: Signal Processing |

Sherif Eid

I like to make boards and other cool electronics

SKILLS

C/C++ | Python | kicad |

AREA OF EXPERTISE

Analog | System-PCB |

Mustafa Sami

SKILLS

Cadence Virtuoso | Calibre | Matlab | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Communication | Circuits: Filters | Circuits: Power Management |

Don Morgan

SKILLS

C/C++ | Python | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

System: FPGA Programming |

AT

SKILLS

Python |

AREA OF EXPERTISE

Analog: Design |

Paulo Roberto Bueno de Carvalho

Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: FPGA Programming | System: PCB |

Ananth Chellappa

Analog Designer

SKILLS

Analog CMOS Circuit | Analog IC Design | Circuit Design | Perl | Python |

AREA OF EXPERTISE

Analog IC | Analog IC Design | Analog-Amplifiers | Analog-Modeling | Analog-Simulation | Analog-ADC | Analog-LDO | Analog-SMPS |

Hossam Hassan

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming | System: PCB |

Taimur Rabuske

I am a senior researcher in INESC-ID, Lisbon.

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Octave | Python | Software Developer | Spectre |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Signal Processing |

Ernesto Conde

Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | ngspice | Python | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Hasan Mohamed

SKILLS

C/C++ | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Digital: RTL | Digital: Synthesis | Miscellaneous: Neural Networks | System: FPGA Programming |

Salvatore M. Cherchi

SKILLS

C/C++ | Eagle CAD | Electric CAD | Matlab | ngspice | Python | System Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Business: Design Services | Circuits: Communication | Circuits: Memory | Circuits: Signal Processing | Miscellaneous: Cryptography | SoC: ESD | SoC: Floorplanning | System: Fabrication Process | System: Power Integrity | System: Signal Integrity |

Mahmoud Abdelgawad

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Digital: DFT | Digital: RTL | Digital: Synthesis | Digital: Verification |

Dominic Chan

SKILLS

Python |

AREA OF EXPERTISE

Analog: Design |

Martin Simlastik

digital ASIC designer with 10+ yrs experience

SKILLS

Electric CAD | Matlab | Perl | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

IC |

Mahadev Shiva Bhat

I am enthusiastic student in SoC designing

SKILLS

C/C++ | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Francisco Gomes

SKILLS

C/C++ | Python |

AREA OF EXPERTISE

Academic: Student |

sto

Principle Engineer at efabless corporation

SKILLS

C/C++ | Cadence Virtuoso | Diva | Electric CAD | Magic CAD | Netgen | ngspice | Octave | Python | SKILL | Software Developer | Tcl/Tk |

AREA OF EXPERTISE

AWS infrastructure | CAD: Scripting | CAD: Tool Development | Design Automation | EDA | Linux | physical design verification | unix system administration |

Thiago Coura

SKILLS

Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

SoC: Verification |

Sandeep Gunturi

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Florian Ballenegger

Analog and mixed-signal IC designer.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | ngspice | Python | Spectre |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | CAD: Scripting | Circuits: Power Management | SoC: ESD |

Viraj Bharadwaj Korede

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Octave | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Jhalak Sharma

SKILLS

Cadence Virtuoso | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Research |

Tigran Poghosyan

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Hercules | Python | Tcl/Tk |

AREA OF EXPERTISE

Analog: Layout | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification |

Monika Sidde

Right now, I am working on physical design of ASIC.

SKILLS

C/C++ | Python | Verilog |

AREA OF EXPERTISE

Academic: Research |

RISIKESH Rk

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Python |

AREA OF EXPERTISE

Academic: Student | System: FPGA Programming |

Martin Elaskar

Electronic engineering student. 24 years old. Currently doing a LNA design as thesis.

SKILLS

C/C++ | Matlab | Python |

AREA OF EXPERTISE

Academic: Student |

Nicholas Harvey

SKILLS

C/C++ | Python |

AREA OF EXPERTISE

Academic: Teaching |

Lalith Kota

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Octave | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Student |

Kenneth

SKILLS

C/C++ | Eagle CAD | ngspice | Python |

AREA OF EXPERTISE

Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing |

Rakesh Singanahalli

Hello I am Rakesh , I am pursuing my Under Graduation in Electronics and Communication Engineering at KLE Technological University, Hubballi. I am looking ahead work in Digital VLSI Domain. :D

SKILLS

C/C++ | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: Synthesis | Digital: Verification |

Pranav Tippa

SKILLS

C/C++ | Leadership | Python |

AREA OF EXPERTISE

Academic: Student |

Mahesh Bhat K

Still a Bachelor student..Trying to get know more always!!

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Aidan Goettsch

SKILLS

C/C++ | Python | Software Developer |

AREA OF EXPERTISE

Academic: Student |

Aled Cuda

I'm a physics major studying at UC Berkeley interested in accelerating research and computational workloads with modern VLSI and FPGA tech.

SKILLS

Chisel | KiCAD | LiteX | Python | Software Developer | SpinalHDL | Verilog |

AREA OF EXPERTISE

Academic: Research | System: FPGA Programming |

Amruthraj Koparde

SKILLS

C/C++ | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Sultan Bepari

Hello I'm sultan, and I'm from KLE technological University hubli and I'm very exited to do this course on picorisc.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Nithin Angadi

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Gourav Saini

SKILLS

Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Adithya (AJ) Naresh

SKILLS

C/C++ | Eagle CAD | Matlab | Python | Scilab | Verilog |

AREA OF EXPERTISE

System: Test Programming |

ABHISHEK RAGHAVENDRA PAMADI

I am Abhishek Pamadi , studying engineering in KLE Technological University, I have keen interest in VLSI domain

SKILLS

Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Aditya Gupta

SKILLS

Cadence Virtuoso | Matlab | Python | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers |

Titouan Quennet

SKILLS

C/C++ | Python |

AREA OF EXPERTISE

Academic: Student |

Venkata Anurag N/A Atmakuri

I’m an engineer always looking to learn, optimize and automate. I work on data analytics to provide deep insights into hardware designs, particularly physical design flow. Exploring areas to facilitate design engineers in taking data driven decisions for faster design turnaround times. I like to think about life. I like experimenting with different techniques (using software tools and meditation) to optimize my day and work effectively. In my free time, I’m learning Web Programming to build my own blog. I know there are templates and websites but where’s the fun and learning if you don’t do it from scratch? I like mentoring students on how to approach career and life in general.

SKILLS

Python | System Verilog | Tcl/Tk | Cadence |

AREA OF EXPERTISE

Digital: Placement and Routing |

Ankit wahane

pursuing pg in vlsi system design from vnit

SKILLS

ngspice | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Nathan Tang

Student at Poolesville High School interested in computer science and engineering

SKILLS

C/C++ | Matlab | Python |

AREA OF EXPERTISE

Academic: Student |

ganesh deshmukh

SKILLS

Eagle CAD | Python |

AREA OF EXPERTISE

Academic: Student |

Tharakram Korripadu

SKILLS

C/C++ | Perl | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Arjun Rakheja

SKILLS

Python |

AREA OF EXPERTISE

Academic: Student |

Vishal Sao

SKILLS

Cadence Virtuoso | Magic CAD | Netgen | ngspice | Python |

AREA OF EXPERTISE

Analog: Design | Analog: Layout |

Francisco Brito Filho

Electronic Engineer with experience in RF/AMS IC Design and other electronics and telecommunications projects. Served in working groups and also as leader. Has also experience in entrepreneurship. PhD in Microelectronics. Currently Adjunct Professor at Federal University of Semi-Árid Region - UFERSA and Head of LIEB/LAMERF Research Labs where develop R&D projects in the areas of instrumentation, biomedical engineering, RF/MW circuits and microelectronics.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Leadership | Matlab | ngspice | Octave | Python | Spectre | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Sensors | Miscellaneous: Neural Networks | System: FPGA Programming | RF Circuits and Systems | RF IC Design | Microwaves |

Temitope Olarinde

SKILLS

C/C++ | Python |

AREA OF EXPERTISE

Academic: Research |

Joshua Stevens

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Eagle CAD | Python | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research |

Denise Cocco

President and CEO

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Matlab | Perl | Python | SKILL | Spectre | SPICE Opus | System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Foundry Services | Business: Packaging | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: Fabrication Process | System: Packaging | System: Quality Assurance |

Projjal Gupta

SKILLS

C/C++ | Eagle CAD | Python |

AREA OF EXPERTISE

Academic: Research |

Sreenivasan Jouly

SKILLS

C/C++ | Matlab | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Prachi Mrudula

Be the someone among everyone who pioneers everyone to be a someone !

SKILLS

Cadence Virtuoso | Magic CAD | Netgen | ngspice | Python | Spectre |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation |

Ricardo Godinez

SKILLS

Python | Tcl/Tk | Verilog | DFT |

AREA OF EXPERTISE

Digital: DFT | Digital: RTL |

Pascal Sossou

I like Basketball

SKILLS

Python | Java | LISP |

AREA OF EXPERTISE

Academic: Student |

Lucas Gonzalez-Rey

SKILLS

Leadership | Python |

AREA OF EXPERTISE

Academic: Student |

Tutu Ajayi

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Research |

Pavan Kumar Kori

current I am doing postgraduation in a Micro and Nanoelectronics

SKILLS

Cadence Virtuoso | ngspice | Python |

AREA OF EXPERTISE

Academic: Student |

P Santosh Kumar Patra

I am a final year Masters student of NIT Rourkela, I am interested in SoC designing using RISCV ISA

SKILLS

C/C++ | Matlab | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Pablo Mendoza Ponce

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Python | Spectre | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research |

Nataraj Pinakapani

SKILLS

Cadence Virtuoso | Calibre | ngspice | Python |

AREA OF EXPERTISE

Analog: Layout | CAD: Tool Development |

Vivek Parmar

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | ngspice | Octave | Python | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Modeling | Analog: Simulation | Circuits: Memory | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Test Equipment |

Alberto Gancedo

SKILLS

Cadence Virtuoso | Calibre | Matlab | Python | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Communication | Circuits: Sensors |

Risto Pejasinovic

SKILLS

C/C++ | Eagle CAD | Electric CAD | ngspice | Python | Software Developer | System Verilog | System-C | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Yaswanth Kumar Cherivirala

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | Spectre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Modeling | Circuits: Power Management |

Vernon Greer

Analog IC Design Engineer with considerable expertise in mid- to high-frequency transistor-level design in the semiconductor industry, including clock synthesis, radio frequency circuitry (RF), and memory circuitry design. Experience also includes testing at board- and wafer-level, test automation, and simulation scripting.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Matlab | Perl | Python | SKILL | Spectre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Analog: Verification | CAD: Scripting | Circuits: Communication | Circuits: Memory |

Gustavo Linhares

i'm an eletronic engineer there are studing to became an IP desing

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Circuits: Signal Processing | System: FPGA Programming |

Adrian Freed

I am designed mixed signal ICs for Music, Audio, IoT and sensor applications.

SKILLS

C/C++ | Eagle CAD | Matlab | ngspice | Perl | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Modeling | Business: Design Services | CAD: Tool Development | Circuits: Filters | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Test Equipment |

Bittu N

SKILLS

C/C++ | Eagle CAD | Matlab | ngspice | Octave | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research |

Mohit R

Graduate equipped with a Bachelor of Engineering in Electronics and communication with a concentration in Semiconductor and VLSI design with hands-on experience in CAD tools and to join a reputable organization to begin a fulfilling, lifelong career.

SKILLS

C/C++ | Cadence Virtuoso | Electric CAD | Python | SKILL | Verilog |

AREA OF EXPERTISE

Analog: Layout |

Ippei Akita

An analog mixed-signal circuit designer for low-power precision sensor interfaces. See https://staff.aist.go.jp/ippei.akita/

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Python | Spectre | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: Chip Editing | System: PCB | System: Test Equipment |

Ha Tran

SKILLS

Cadence Virtuoso | Calibre | Python | Verilog |

AREA OF EXPERTISE

Analog: Design | Circuits: Memory | Digital: RTL |

Aliaa Fouli

Digital Logic Designer

SKILLS

Python | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Greg Cook

SKILLS

Python | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

System: PCB |

Andrew Vella

SKILLS

Leadership | Python |

AREA OF EXPERTISE

System: Fabrication Process |

Andrew Selasi Agbemenu

Lecturer at the Department of Computer Engineering, Kwame Nkrumah University of Science and Technology, KNUST. My primary interest is in analog and mixed-signal design.

SKILLS

Cadence Virtuoso | Calibre | Matlab | ngspice | Python | Spectre | VHDL |

AREA OF EXPERTISE

Academic: Teaching |

Joseph Kiniry

Dad. Partner. Scientist. Activist. Maker. — He/His

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Leadership | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | Bluespec | Chisel | EDA R&D |

AREA OF EXPERTISE

Academic: Research | Business: Design Services | Business: Management | CAD: Tool Development | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: Quality Assurance | System: Test Programming | Miscellaneous: Formal Methods |

Karthekeyan Periasamy

SKILLS

Python |

AREA OF EXPERTISE

Academic: Student |

chandan shankar M

SKILLS

C/C++ | Matlab | Python | Scilab | Verilog |

AREA OF EXPERTISE

Academic: Student |

Rob Jefferson

Software engineer who's increasingly interested in hardware and ISAs.

SKILLS

C/C++ | Perl | Python |

AREA OF EXPERTISE

System: FPGA Programming |

Pepijn de Vos

SKILLS

C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | Spectre | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Digital: RTL | Digital: Synthesis |

Rahul Behl

SKILLS

Perl | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification |

KASHISH GOYAL

SKILLS

Python | Scilab | SKILL | Software Developer |

AREA OF EXPERTISE

Academic: Student |

KUMAR SAKET

SKILLS

C/C++ | Python | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis |

Madhu Siddalingaiah

Artificial Intelligence/Machine Learning • Big Data • Internet of Things • Product Development

SKILLS

Eagle CAD | Leadership | LTspice | Python | Software Developer | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Analog: Verification |

Kiran Prasad Kanaparthi

SKILLS

C/C++ | Leadership | Perl | Python | System Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | Digital: Verification |

Saffet BULUT

SKILLS

C/C++ | Python | System Verilog |

AREA OF EXPERTISE

Academic: Student |

Hanssel Morales

SKILLS

C/C++ | Cadence Encounter | Chisel | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification |

Anish Singhani

SKILLS

C/C++ | Chisel3 | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Dennis Restle

SKILLS

C/C++ | Python | Scilab | Software Developer | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | System: FPGA Programming | System: PCB |

Akil M

Undergraduate Student at NIT-Trichy

SKILLS

Eagle CAD | Matlab | ngspice | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

H Prameeth

An engineer looking forward to making a career in digital vlsi design

SKILLS

Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Anton Moiseev

Analog Circuit Design

SKILLS

ngspice | Python | SPICE Opus |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation |

Michael Irschick

Product/Project manager

SKILLS

Python | Software Developer |

AREA OF EXPERTISE

Business: Management |

Damien Bonneau

R&D Engineer, interest in synthesis and verification software for electronics and photonics hardware

SKILLS

Python | Software Developer | VHDL |

AREA OF EXPERTISE

Academic: Research | CAD: Scripting | CAD: Tool Development | System: FPGA Programming |

Ahmed El-Omla

SKILLS

C/C++ | Python | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

Miscellaneous: Cryptography |

Juha Häkkinen

Ph.D. in electrical engineering, 25 years experience in mixed-signal IC design

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Diva | Eagle CAD | Matlab | Octave | Perl | Python | Scilab | Spectre |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Circuits: Communication | Digital: Placement and Routing | Digital: Synthesis |

Ben R

I am a High School Student, Entry Electrical Engineer, and Computer Scientist I love to tinker with stuff and to innovate new ideas.

SKILLS

C/C++ | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Student | Circuits: Signal Processing |

Guy Hutchison

SKILLS

Leadership | Python | Verilog |

AREA OF EXPERTISE

Business: Management | Digital: RTL | Digital: Verification |

Furkan Ciylan

SKILLS

C/C++ | Matlab | Python | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Business: Packaging | Business: Patents | Business: PCB Manufacture |

Mayuresh Rajwadkar

Silicon Entrepreneur with extensive experience in Digital Physical Design, EDA and HPC Infrastructures for Electronic Design.

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Hercules | Leadership | Perl | Python | Spectre | Verilog |

AREA OF EXPERTISE

Business: Design Services | Business: Sales | CAD: Scripting | Digital: Placement and Routing | Digital: Verification | SoC: Floorplanning | System: PCB |

ADITYA ANAND

SKILLS

Cadence Encounter | Matlab | ngspice | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: FPGA Programming | System: Signal Integrity |

Nelson Rodriguez

An enthusiast of the Open Source World.

SKILLS

C/C++ | Matlab | Python | Verilog | Linux |

AREA OF EXPERTISE

Academic: Student |

Edwil Fernandes

SKILLS

C/C++ | Electric CAD | Matlab | ngspice | Python | Scilab | Verilog |

AREA OF EXPERTISE

Academic: Student |

Hene Stuchi Saud

SKILLS

C/C++ | Cadence Virtuoso | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Amro Tork

More than 14 years of experience in Electronic Design Automation roles with leading industry companies like Intel, Samsung and others. Have a strong background in EDA best practices and technologies like DRC, LVS, XRC, PERC and others. Have a mixed background in circuit. design, data science and programming with emphasis on data analysis for microchip design. Have strong background leading project deliveries to fortune 100 companies in the world. B.Sc. in Electrical Engineering from faculty of Engineering, Ain Shams University, Cairo, Egypt.

SKILLS

C/C++ | Calibre | Eldo | Magic CAD | ngspice | Python |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | CAD: Scripting | CAD: Tool Development | Circuits: Signal Processing |

Matt Long

I am a software developer for Efabless. I live in San Francisco, CA. I play guitar, bass, and drums. I love playing and listening to all types of music.

SKILLS

Python | Software Developer |

AREA OF EXPERTISE

Security |

Nathan Turner

SKILLS

Matlab | Octave | Python |

AREA OF EXPERTISE

Analog: Design |

RAHUL SREEKUMAR

I am currently a second year PhD. student working in the field of Electrical Engineering at the University of Virginia. My research interests include Analog/Mixed Signal circuit design, Asynchronous computing hardware design, stochastic computing and Ultra-Wide Band transmission circuits

SKILLS

Cadence Virtuoso | Calibre | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Research |

Halid Altuner

SKILLS

Python | Software Developer | System-C | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing |

Junichiro Kadomoto

PhD student at UTokyo

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Python | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Student |

Thomas Parry

Mixed-signal designer

SKILLS

Cadence Virtuoso | Calibre | Matlab | Netgen | ngspice | Python | Spectre | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Digital: RTL | Digital: Verification |

Mustafa Khairallah

I am a Ph.D. student at the School of Physical and Mathematical Sciences, NTU, Singapore. I co-designed the Romulus and Remus families of lightweight authenticated encryption modes with Tetsu Iwata, Kazuhiko Minematsu and Thomas Peyrin, which are the basis of three candidates for the NIST Lightweight Cryptography Competition. Previously, I got my BSc. in Electronics Engineering from Alexandria University, Egypt. My main research focus is the practical aspects of Symmetric Key Cryptography, which includes: Physical Security, Hardware Implementations, Practical Cryptanalysis and Primitive Design. Previous research projects also included the acceleration of Fully Homomorphic Encryption and Design and Verification of Digital Circuits.