I am a software developer, trying to learn about hardware design
I am a senior researcher in INESC-ID, Lisbon.
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
Principle Engineer at efabless corporation
Physical design engineer
An experimental physicist through sensor and instrumentation development.
Expert in embedded and mobile applications since 2003. Has many years of experience in software and hardware development, effective team management. Excellent in the research and development, technology findings and implementations.
I'm an engineer with experience in analog IC design both in private companies as well as academia. Experienced in design of delay locked loop(DLL), clock recovery, field detectors, voltage limiters, operational amplifiers, current mirrors, bandgap reference and so on.
More than 14 years of experience in Electronic Design Automation roles with leading industry companies like Intel, Samsung and others. Have a strong background in EDA best practices and technologies like DRC, LVS, XRC, PERC and others. Have a mixed background in circuit. design, data science and programming with emphasis on data analysis for microchip design. Have strong background leading project deliveries to fortune 100 companies in the world. B.Sc. in Electrical Engineering from faculty of Engineering, Ain Shams University, Cairo, Egypt.
Professor of CSE at UC Santa Cruz
I am an Associate Professor teaching VLSI design, hardware security, and digital circuit design at Drexel University. My research interests include analysis, modeling, and design methodologies for high performance digital and mixed-signal integrated circuits, power management for SoC and microprocessor circuits, hardware security, including digital and analog obfuscation and Trojan detection, and electric and thermal modeling and characterization, signal and power integrity, and power and clock delivery for heterogeneous 2-D and 3-D circuits.
PhD student working on a superconducting FPGA design aiming to work on neuromorphic computing in the future.
Program manager with more than 25 years experience in the semiconductor industry. Expertise in EDA tools, analogue, RF and high-voltage PDK development, sensor design, design support for electro-magnetic compatibility, ESD and functional safety.
Hello, I'm an IC Designer Analog/RF with digital skills. I worked mainly on PLL for mobile tranceivers. I used to work on Cadence Design flow for 20 years.
I am designed mixed signal ICs for Music, Audio, IoT and sensor applications.
Dad. Partner. Scientist. Activist. Maker. — He/His
For most of my career, I was a CAD technology innovator and CAD system architect at Intel Corporation. I signed up recently for a Udemy class called "VSD - Making the Raven Chip: How to Design a RISC-V SoC." The class pointed me to Efabless.
ASIC design engineer at Google advancing high-level synthesis and next-generation computer architectures.