profiles search for area of expertise: System: Fabrication Process
13 results
Azhar Din
Passionate about engineering and electronics. Love teaching and mentoring. Highly experience in analogue and RF electronics and enjoy managing projects.
SKILLS
- Cadence Virtuoso | Calibre | Diva | Leadership | Matlab | Perl | Spectre |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Management | CAD: Scripting | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Fabrication Process | System: PCB | System: Test Equipment |
David Garner
An experienced mixed-signal IC design engineer / design manager with over 25 years experience. Has design and led the design of multiple mixed-signal ICs through to tapeout and silicon verification. Also experienced with the delivery of IP blocks. Worked across multiple market sectors.
SKILLS
- Cadence Virtuoso | Diva | Leadership | Matlab | Octave | SKILL | Spectre |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Management | Business: Patents | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: Fabrication Process | System: Power Integrity | System: Quality Assurance | System: Signal Integrity | System: Test Equipment |
Amit Prakash Gonnagar
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Electric CAD | Magic CAD | ngspice | Perl | Spectre | System Verilog | Tcl/Tk | Verilog |
Amudhan Balasubramanian
Over 25+ years of experience Silicon Engineer with focus on taking a Silicon from GDS2 to PRQ. Involved in Wafersort testing, Packaging, Packaging Testing, Silicon Characterisation - Electrical & Functional, Package Qualification, Reliablity testing and Yield management
SKILLS
- Leadership | Python | Verilog |
ardencaple
Semiconductor professional with 40 years experience.
I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.
AREA OF EXPERTISE
Salvatore M. Cherchi
SKILLS
- C/C++ | Eagle CAD | Electric CAD | Matlab | ngspice | Python | System Verilog |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Business: Design Services | Circuits: Communication | Circuits: Memory | Circuits: Signal Processing | Miscellaneous: Cryptography | SoC: ESD | SoC: Floorplanning | System: Fabrication Process | System: Power Integrity | System: Signal Integrity |
Gangadhar Yedida
I am studying Electronics and communication engineering (Integrated MTech) in International institute of information technology, Bangalore . I want to get access to tools for course project .
SKILLS
- Verilog |
AREA OF EXPERTISE
Denise Cocco
President and CEO
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Matlab | Perl | Python | SKILL | Spectre | SPICE Opus | System Verilog | Tanner L-Edit | Verilog |
AREA OF EXPERTISE
- Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Foundry Services | Business: Packaging | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: Fabrication Process | System: Packaging | System: Quality Assurance |
Andrew Vella
SKILLS
- Leadership | Python |
AREA OF EXPERTISE
Pratika Tripathi
I am Pratika Tripathi. I am in my final year of Btech. I am very interested in physical designing of IC. I had even taken 3 courses of kunal ghosh sir on physical design, stay, and cts.
I am doing my final year project in physical design.
AREA OF EXPERTISE
Alexander Stanitzki
Analog/MS/RF IC designer
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Diva | Leadership | Python | SKILL | Spectre | Verilog |
Peter Bermel
DR. PETER BERMEL is an associate professor of Electrical and Computer Engineering at Purdue University. He is the PI for the SCALE project, which aims to perform workforce development in microelectronics. His research focuses on improving the performance of photovoltaic, thermophotovoltaic, and microelectronic systems using the principles of nanophotonics. Key enabling techniques for his work include electromagnetic and electronic theory, modeling, simulation, fabrication, and characterization.
SKILLS
AREA OF EXPERTISE
Patrick Degenaar
I am a professor of Neuroprosthetics at Newcastle University. My primary interest is in developing implantable medical devices to treat neurological conditions.
SKILLS
- Cadence Virtuoso | Leadership | Matlab | Octave |
