Tag results for: area of expertise

Mauricio De Carvalho

SKILLS

C/C++ | Cadence Encounter | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Business: Design Services | Circuits: Microcontrollers | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming |

Azhar Din

Passionate about engineering and electronics. Love teaching and mentoring. Highly experience in analogue and RF electronics and enjoy managing projects.

SKILLS

Cadence Virtuoso | Calibre | Diva | Leadership | Matlab | Perl | Spectre |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Management | CAD: Scripting | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Fabrication Process | System: PCB | System: Test Equipment |

Preetham Lakshmikanthan

SKILLS

C/C++ | System Verilog |

AREA OF EXPERTISE

Circuits: Power Management | Digital: Verification | SoC: Verification |

Ronan BARZIC

Principal Engineer at ONiO AS

SKILLS

C/C++ | Magic CAD | ngspice | Python | System-C | Verilog |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Power Management | Digital: RTL | Digital: Verification | Miscellaneous: Neural Networks | SoC: Verification |

Gautam Navapara

SKILLS

C/C++ | Cadence Encounter | Calibre | Magic CAD | Perl | Tcl/Tk |

AREA OF EXPERTISE

Digital: Placement and Routing | SoC: Floorplanning | SoC: Verification |

An experienced mixed-signal IC design engineer / design manager with over 25 years experience. Has design and led the design of multiple mixed-signal ICs through to tapeout and silicon verification. Also experienced with the delivery of IP blocks. Worked across multiple market sectors.

SKILLS

Cadence Virtuoso | Diva | Leadership | Matlab | Octave | SKILL | Spectre |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Management | Business: Patents | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: Fabrication Process | System: Power Integrity | System: Quality Assurance | System: Signal Integrity | System: Test Equipment |

Vishal Prafulkumar Katigar

Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)

SKILLS

C/C++ | Perl | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers | Circuits: Sensors | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: PCB |

Ankit Agrawal

I am VLSI Design & Verification Engineer.

SKILLS

Aldec RivieraPro | C/C++ | Digital Electronics | System Verilog | UVM | Verilog | Xilinx ISE |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | SoC: Verification |

Ira Chayut

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | SoC: Verification |

Santhosh

IP & SoC Verification Engineer

SKILLS

Perl | System Verilog | Verilog | VHDL | UVM |

AREA OF EXPERTISE

Digital: Verification | SoC: Verification |

Sagar Jadhav

SKILLS

System Verilog | Verilog |

AREA OF EXPERTISE

Digital: Verification | SoC: Verification |

ROSHAN ALI SK

SKILLS

C/C++ | Cadence Virtuoso |

AREA OF EXPERTISE

SoC: ESD | SoC: Floorplanning | SoC: Verification |

Chaitanya Parashar

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | SoC: Verification |

Sajal Goyal

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | SoC: Verification |

Luc Wong

I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |

David Fleischer

Technology development in intergrated analog circuits. I'm available to design analog and mixed-signal circuits as an external contractor.

SKILLS

A/D converter | Analog and mixed-signal IP circuit design | Audio | Bandgap reference | CMOS Image Sensor | Computer arithmetic | Integration | Nonvolatile memory | Operational amplifier | Sigma-delta | SPICE simulations | Video DAC |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Patents | Business: PCB Manufacture | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Miscellaneous: Cryptography | SoC: Verification | System: PCB |

pranay reddy

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification |

jatindersingh

SKILLS

Analog/Digital Circuit Design | C/C++ | Electric CAD | Magic CAD | ngspice | Python | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog-SMPS | Analog: Simulation | Analog: Verification | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital-DV | Digital-RTL | Digital: DFT | Digital: Placement and Routing | Miscellaneous: Neural Networks | SOC-DV | SoC: ESD | SoC: Floorplanning | SoC: Verification | System-DSP | System: Chip Editing | System: FPGA Programming |

Srimanth

SKILLS

Eagle CAD | Python | Software Developer | Verilog |

AREA OF EXPERTISE

SoC: Verification |

Anton Balbekov

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Leadership | Netgen | Python | SKILL | Software Developer | Spectre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: Power Integrity |

eldho george

SKILLS

Cadence Virtuoso | Matlab | Perl | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | SoC: Verification |

Nambi

SKILLS

C/C++ | ngspice | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Verification | Business: Design Services | CAD: Tool Development | Digital: Verification | SoC: Verification |

Marco Merlin

Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Octave | Python | SKILL | System Verilog | Verilog | VHDL | wifi | bluetooth | LTE |

AREA OF EXPERTISE

Analog: Verification | Circuits: Communication | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Neural Networks | SoC: Verification | System: PCB | System: Test Equipment | System: Test Programming |

ardencaple

Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.

SKILLS

C/C++ | Leadership | Python | Verilog | VHDL | DC | PrimeTime |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: Fabrication Process | System: FPGA Programming | Digital audio | IoT | Soc | Mixed Signal |

Paulo Roberto Bueno de Carvalho

Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: FPGA Programming | System: PCB |

Hossam Hassan

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming | System: PCB |

Bob Ledzius

35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.