profiles search for area of expertise: SoC: Verification
43 results
Mauricio De Carvalho
SKILLS
- C/C++ | Cadence Encounter | Software Developer | System Verilog | Verilog | VHDL |
Azhar Din
Passionate about engineering and electronics. Love teaching and mentoring. Highly experience in analogue and RF electronics and enjoy managing projects.
SKILLS
- Cadence Virtuoso | Calibre | Diva | Leadership | Matlab | Perl | Spectre |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Management | CAD: Scripting | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Fabrication Process | System: PCB | System: Test Equipment |
Preetham Lakshmikanthan
SKILLS
- C/C++ | System Verilog |
AREA OF EXPERTISE
Ronan BARZIC
Principal Engineer at ONiO AS
AREA OF EXPERTISE
Gautam Navapara
AREA OF EXPERTISE
David Garner
An experienced mixed-signal IC design engineer / design manager with over 25 years experience. Has design and led the design of multiple mixed-signal ICs through to tapeout and silicon verification. Also experienced with the delivery of IP blocks. Worked across multiple market sectors.
SKILLS
- Cadence Virtuoso | Diva | Leadership | Matlab | Octave | SKILL | Spectre |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Management | Business: Patents | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: Fabrication Process | System: Power Integrity | System: Quality Assurance | System: Signal Integrity | System: Test Equipment |
Vishal Prafulkumar Katigar
Trained in ASIC verification from Maven silicon Bengaluru
Also having experience in embedded domain (PCB layout design)
SKILLS
- C/C++ | Perl | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Ankit Agrawal
I am VLSI Design & Verification Engineer.
SKILLS
- Aldec RivieraPro | C/C++ | Digital Electronics | System Verilog | UVM | Verilog | Xilinx ISE |
AREA OF EXPERTISE
Ira Chayut
AREA OF EXPERTISE
Sagar Jadhav
SKILLS
AREA OF EXPERTISE
ROSHAN ALI SK
SKILLS
AREA OF EXPERTISE
Chaitanya Parashar
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Sajal Goyal
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Luc Wong
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |
David Fleischer
Technology development in intergrated analog circuits.
I'm available to design analog and mixed-signal circuits as an external contractor.
SKILLS
AREA OF EXPERTISE
- Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Patents | Business: PCB Manufacture | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Miscellaneous: Cryptography | SoC: Verification | System: PCB |
pranay reddy
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Verilog |
AREA OF EXPERTISE
jatindersingh
SKILLS
- Analog/Digital Circuit Design | C/C++ | Electric CAD | Magic CAD | ngspice | Python | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | VLSI/ASIC and SoC Development |
AREA OF EXPERTISE
- Analog-SMPS | Analog: Simulation | Analog: Verification | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital-DV | Digital-RTL | Digital: DFT | Digital: Placement and Routing | Miscellaneous: Neural Networks | SOC-DV | SoC: ESD | SoC: Floorplanning | SoC: Verification | System-DSP | System: Chip Editing | System: FPGA Programming |
Srimanth
SKILLS
- Eagle CAD | Python | Software Developer | Verilog |
AREA OF EXPERTISE
Anton Balbekov
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Leadership | Netgen | Python | SKILL | Software Developer | Spectre | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: Power Integrity |
eldho george
SKILLS
- Cadence Virtuoso | Matlab | Perl | System Verilog | Verilog |
AREA OF EXPERTISE
Nambi
AREA OF EXPERTISE
Marco Merlin
Electronics Engineer with 10 years experience in microelectronics and research.
Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms.
Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to.
During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.
SKILLS
AREA OF EXPERTISE
ardencaple
Semiconductor professional with 40 years experience.
I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.
AREA OF EXPERTISE
Paulo Roberto Bueno de Carvalho
Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes.
He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.
SKILLS
- C/C++ | Cadence Encounter | Python | System Verilog | Verilog | VHDL |
Hossam Hassan
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming | System: PCB |
Bob Ledzius
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
SKILLS
- C/C++ | Leadership | Matlab | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Business: Design Services | Business: Management | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: PCB |
Pascal Buchschacher
designing mixed-mode ASICs since 1986 :-)
SKILLS
- Cadence Virtuoso | Leadership | Matlab | Spectre | Verilog | VHDL |
AREA OF EXPERTISE
Thiago Coura
SKILLS
- Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
kowtarapu chaitanya
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Verilog | ltspice |
AREA OF EXPERTISE
Tigran Poghosyan
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Hercules | Python | Tcl/Tk |
AREA OF EXPERTISE
Denise Cocco
President and CEO
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Matlab | Perl | Python | SKILL | Spectre | SPICE Opus | System Verilog | Tanner L-Edit | Verilog |
AREA OF EXPERTISE
- Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Foundry Services | Business: Packaging | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: Fabrication Process | System: Packaging | System: Quality Assurance |
Geethanand N
Ex intel professional with over 5 years of experience in front end Vlsi
SKILLS
- Perl | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
vinay k s
Verification engineer and quick learner and really enthusiastic to learn new things
SKILLS
- Perl | System Verilog | Verilog |
AREA OF EXPERTISE
Joseph Kiniry
Dad. Partner. Scientist. Activist. Maker. — He/His
SKILLS
- C/C++ | Cadence Virtuoso | Eagle CAD | Leadership | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | Bluespec | Chisel | EDA R&D |
AREA OF EXPERTISE
- Academic: Research | Business: Design Services | Business: Management | CAD: Tool Development | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: Quality Assurance | System: Test Programming | Miscellaneous: Formal Methods |
Rahul Behl
SKILLS
- Perl | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Chaitanya CVS
SKILLS
- Perl | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
Anurag Darbari
SubIP and SoC Design Verification Engineer. Extends to running Full Chip Emulation on Palladium and Protium Platforms.
SKILLS
- System Verilog | uvm | Verilog |
AREA OF EXPERTISE
Mustafa Khairallah
I am a Ph.D. student at the School of Physical and Mathematical Sciences, NTU, Singapore. I co-designed the Romulus and Remus families of lightweight authenticated encryption modes with Tetsu Iwata, Kazuhiko Minematsu and Thomas Peyrin, which are the basis of three candidates for the NIST Lightweight Cryptography Competition. Previously, I got my BSc. in Electronics Engineering from Alexandria University, Egypt. My main research focus is the practical aspects of Symmetric Key Cryptography, which includes: Physical Security, Hardware Implementations, Practical Cryptanalysis and Primitive Design. Previous research projects also included the acceleration of Fully Homomorphic Encryption and Design and Verification of Digital Circuits.
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL | perl |
AREA OF EXPERTISE
Bilal Zafar
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Leadership | Magic CAD | Matlab | ngspice | Perl | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Shiwani Gurunathrao Darekar
SKILLS
AREA OF EXPERTISE
Leonidas Kosmidis
I'm a Senior Researcher at the Barcelona Supercomputing Center and Junior Faculty at Polytechnic University of Catalonia (UPC). I'm the recipient of the RISC-V Educator of the Year Award 2019, for the advanced graduate course Processor Design I'm teaching at UPC, which is focused on the design of high-performance safety-critical systems. I'm the PI of the GPU4S project funded by the European Space Agency (ESA) in which we are investigating the applicability of embedded GPUs in space.
SKILLS
- C/C++ | Electric CAD | Leadership | Software Developer | Verilog |
AREA OF EXPERTISE
Ahmed Yiwere
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | ngspice | Perl | Python | System Verilog | Verilog | VHDL |
