Tag results for: area of expertise

Daniel J Wisehart

More than 25 years in FPGA design

SKILLS

C/C++ | Perl | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | SoC: Floorplanning | System: FPGA Programming |

Praneeth

SKILLS

Cadence Encounter | Cadence Virtuoso | Hercules | Perl | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Memory | Circuits: Power Management | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning |

Azhar Din

Passionate about engineering and electronics. Love teaching and mentoring. Highly experience in analogue and RF electronics and enjoy managing projects.

SKILLS

Cadence Virtuoso | Calibre | Diva | Leadership | Matlab | Perl | Spectre |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Management | CAD: Scripting | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Fabrication Process | System: PCB | System: Test Equipment |

CHINTADA.GAYATRI

Physical Design Engineer

SKILLS

C/C++ | Calibre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Verification | Business: Management | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Stephane Badel

Physical design engineer

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Eldo | Hercules | Matlab | ngspice | Octave | Perl | SKILL | Spectre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Layout | Analog: Simulation | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Sushma kumari

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SKILLS

Cadence Encounter |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: Verification | SoC: Floorplanning |

Gautam Navapara

SKILLS

C/C++ | Cadence Encounter | Calibre | Magic CAD | Perl | Tcl/Tk |

AREA OF EXPERTISE

Digital: Placement and Routing | SoC: Floorplanning | SoC: Verification |

An experienced mixed-signal IC design engineer / design manager with over 25 years experience. Has design and led the design of multiple mixed-signal ICs through to tapeout and silicon verification. Also experienced with the delivery of IP blocks. Worked across multiple market sectors.

SKILLS

Cadence Virtuoso | Diva | Leadership | Matlab | Octave | SKILL | Spectre |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Management | Business: Patents | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: Fabrication Process | System: Power Integrity | System: Quality Assurance | System: Signal Integrity | System: Test Equipment |

Amit Prakash Gonnagar

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Electric CAD | Magic CAD | ngspice | Perl | Spectre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Circuits: Power Management | Digital: Placement and Routing | Digital: Synthesis | SoC: ESD | SoC: Floorplanning | System: Chip Editing | System: Fabrication Process | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Programming |

ROSHAN ALI SK

SKILLS

C/C++ | Cadence Virtuoso |

AREA OF EXPERTISE

SoC: ESD | SoC: Floorplanning | SoC: Verification |

Fenil

SKILLS

Cadence Encounter | Tcl/Tk |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

RAJA KUMAR MEHTA

Physical Design Engineer

SKILLS

C/C++ | Calibre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Verification | Business: Management | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Bertrand PIGEARD

Hello, I'm an IC Designer Analog/RF with digital skills. I worked mainly on PLL for mobile tranceivers. I used to work on Cadence Design flow for 20 years.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Diva | Matlab | ngspice | Octave | Perl | Python | Scilab | SKILL | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Communication | Circuits: Memory | SoC: Floorplanning |

MUVVA LAKSHMANKUMAR

SKILLS

C/C++ | Cadence Encounter | Perl | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

RASHMI

Physical Design Engineer

SKILLS

C/C++ | Calibre | Matlab | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Sajal Goyal

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | SoC: Verification |

Luc Wong

I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Lakshya Kailkhura

SKILLS

Cadence Encounter |

AREA OF EXPERTISE

CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: ESD | SoC: Floorplanning | System: Signal Integrity |

vyas v

SKILLS

Tcl/Tk |

AREA OF EXPERTISE

SoC: Floorplanning |

pranay reddy

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification |

jatindersingh

SKILLS

Analog/Digital Circuit Design | C/C++ | Electric CAD | Magic CAD | ngspice | Python | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog-SMPS | Analog: Simulation | Analog: Verification | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital-DV | Digital-RTL | Digital: DFT | Digital: Placement and Routing | Miscellaneous: Neural Networks | SOC-DV | SoC: ESD | SoC: Floorplanning | SoC: Verification | System-DSP | System: Chip Editing | System: FPGA Programming |

Sandipan Sinha

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning | System: Signal Integrity |

James Tandon

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eagle CAD | Eldo | Leadership | Magic CAD | Matlab | Octave | Perl | Python | Scilab | Software Developer | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Business: Design Services | CAD: Tool Development | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: Chip Editing | System: FPGA Programming | System: PCB |

Anton Balbekov

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Leadership | Netgen | Python | SKILL | Software Developer | Spectre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: Power Integrity |

bhavik balwani

i am working as physical design engineer

SKILLS

Cadence Encounter |

AREA OF EXPERTISE

SoC: Floorplanning |

Josep Maria Sánchez Chiva

Current working in my PhD at BarcelonaTech.

SKILLS

Cadence Virtuoso | Calibre | Python | Spectre | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Sensors | SoC: Floorplanning | System: FPGA Programming | System: PCB |

Jyothisha

SKILLS

Cadence Encounter |

AREA OF EXPERTISE

SoC: Floorplanning |

Mahmoud Youssuf Ahmad

Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: FPGA Programming |

Camillo

Experienced Analog Design Engineer with strong background in HV CMOS ASICs.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Octave | Perl | Python | SKILL | Spectre |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Power Management | SoC: ESD | SoC: Floorplanning | System: PCB |

Pushkaraksha K M

Physical design engineer with strong expertise in CAD and low power methodologies

SKILLS

Cadence Encounter | Python | Tcl/Tk | Verilog |

AREA OF EXPERTISE

CAD: Tool Development | Digital: Placement and Routing | SoC: Floorplanning |

Paulo Roberto Bueno de Carvalho

Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: FPGA Programming | System: PCB |

Salvatore M. Cherchi

SKILLS

C/C++ | Eagle CAD | Electric CAD | Matlab | ngspice | Python | System Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Business: Design Services | Circuits: Communication | Circuits: Memory | Circuits: Signal Processing | Miscellaneous: Cryptography | SoC: ESD | SoC: Floorplanning | System: Fabrication Process | System: Power Integrity | System: Signal Integrity |

HALIM

Lecturer UiTM

SKILLS

System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Academic: Teaching | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning |

fabien andrade

Graduated with a Micro-electronics Master from Bordeaux university, France, I have now 18 years of experience. Worked in France, England, Belgium and Brazil, within 5 companies. Implemented physical design flows, recruited, trained and supervised trainees to experienced engineers, I have a vast experience in setting up complete flow (2 companies were startups), as well as signing off important design within NXP and CSR, all to successful first time right silicons. Able to work in total independence as well as within a team, I consider myself as optimist, result focused, with attention to detail while keeping a good trade between time to market and risk taking.

SKILLS

Cadence Encounter | Leadership | Tcl/Tk |

AREA OF EXPERTISE

CAD: Scripting | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Chuan Le

SKILLS

Cadence Encounter | Leadership | Synopsys | Physical design |

AREA OF EXPERTISE

Digital: Placement and Routing | SoC: Floorplanning |

Tigran Poghosyan

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Hercules | Python | Tcl/Tk |

AREA OF EXPERTISE

Analog: Layout | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification |

Denise Cocco

President and CEO

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Matlab | Perl | Python | SKILL | Spectre | SPICE Opus | System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Foundry Services | Business: Packaging | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: Fabrication Process | System: Packaging | System: Quality Assurance |

Tung Hoang

R&D Engineer

SKILLS

Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: Floorplanning |

Artur Darbinyan

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Hercules | Leadership | SPICE Opus | Verilog |

AREA OF EXPERTISE

Analog: Layout | Business: Management | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Nickson P Jose

SKILLS

ASIC | Physical Design | STA | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Digital: Placement and Routing | SoC: Floorplanning |

Malcolm Smith

IC designer with more than 25 years post Ph.D. experience. Specialising in RF, RFIC, analog and mixed-signal. Wide experience in Architecture, system and circuit design. RF front-end module design for cellular with CMOS PA. Over 40 patents issued.

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Octave |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | SoC: ESD | SoC: Floorplanning | System: PCB |

Pratika Tripathi

I am Pratika Tripathi. I am in my final year of Btech. I am very interested in physical designing of IC. I had even taken 3 courses of kunal ghosh sir on physical design, stay, and cts. I am doing my final year project in physical design.

SKILLS

veilog | vhdl | asic flow | physical design | sta | fpga | vlsi |

AREA OF EXPERTISE

Academic: Research | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: Fabrication Process | System: FPGA Programming | System: Packaging |

Marc Rose

For most of my career, I was a CAD technology innovator and CAD system architect at Intel Corporation. I signed up recently for a Udemy class called "VSD - Making the Raven Chip: How to Design a RISC-V SoC." The class pointed me to Efabless.