profiles search for area of expertise: Digital: Synthesis
122 results
Kranthi Kumar Pamarthi
I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.
SKILLS
Mauricio De Carvalho
SKILLS
- C/C++ | Cadence Encounter | Software Developer | System Verilog | Verilog | VHDL |
Praneeth
SKILLS
- Cadence Encounter | Cadence Virtuoso | Hercules | Perl | Spectre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Djamel DELLAA
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Eagle CAD | SPICE Opus | Verilog | VHDL |
AREA OF EXPERTISE
Jonathan Richard Robert Kimmitt
Research Associate at University of Cambridge
SKILLS
- Verilog |
AREA OF EXPERTISE
Venkata Nitheesh Kumar Reddy Kethu
AREA OF EXPERTISE
Mohammed Essam Abd El Samee Soliman
I works as junior physical design engineer and I have passion in VLSI field specially in digital IC design. I have experience in writing RTL, test benches and in PnR flow.
AREA OF EXPERTISE
CHINTADA.GAYATRI
Physical Design Engineer
SKILLS
- C/C++ | Calibre | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Vachan U Bharadwaj
A recent graduate student from Syracuse University major in Electrical Engineering with focus in VLSI Designs
SKILLS
- Cadence Encounter | Cadence Virtuoso | Eagle CAD | Perl | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Peter Atkinson
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Stephane Badel
Physical design engineer
SKILLS
AREA OF EXPERTISE
Per Magnus Østhus
AREA OF EXPERTISE
Stephan Ahles
SKILLS
- C/C++ | Cadence Virtuoso | Eldo | Electric CAD | Leadership | Matlab | ngspice | Octave | Python | SKILL | Spectre | Verilog | VHDL |
Menaka Sajjan
SKILLS
- Cadence Encounter | Cadence Virtuoso | Perl | Verilog | VHDL |
AREA OF EXPERTISE
Christoph Maier
Mad Scientist
AREA OF EXPERTISE
Emre Goncu
SKILLS
- Cadence Encounter | Cadence Virtuoso | Matlab | Verilog | VHDL |
AREA OF EXPERTISE
Amit Prakash Gonnagar
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Electric CAD | Magic CAD | ngspice | Perl | Spectre | System Verilog | Tcl/Tk | Verilog |
Vishal Prafulkumar Katigar
Trained in ASIC verification from Maven silicon Bengaluru
Also having experience in embedded domain (PCB layout design)
SKILLS
- C/C++ | Perl | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Semiu A. Olowogemo
AREA OF EXPERTISE
Manoj S
Tech Lead
AREA OF EXPERTISE
harikrishna
Physical Design Engineer
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Rifat Demircioglu
Managing Partner
SKILLS
- C/C++ | Leadership | Matlab | Perl | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Alcides Silveira Costa
AREA OF EXPERTISE
Gordon Aplin
IC Design Engineer
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Magic CAD | ngspice | Perl | Tanner L-Edit | Verilog | VHDL |
AREA OF EXPERTISE
J. Rodriguez
Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.
SKILLS
- C/C++ | System Verilog | System-C | VHDL |
AREA OF EXPERTISE
Fenil
SKILLS
AREA OF EXPERTISE
RAJA KUMAR MEHTA
Physical Design Engineer
SKILLS
- C/C++ | Calibre | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Mohammed Zakir Hussain
SKILLS
- Cadence Encounter | Cadence Virtuoso | Magic CAD | Netgen | ngspice | Spectre | Tanner L-Edit | Verilog | VHDL |
AREA OF EXPERTISE
MUVVA LAKSHMANKUMAR
SKILLS
- C/C++ | Cadence Encounter | Perl | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Muthukumar
SKILLS
- Cadence Virtuoso | Calibre | Eldo | Python | Spectre | Tanner L-Edit | Verilog |
RASHMI
Physical Design Engineer
AREA OF EXPERTISE
Shahbaz Abbasi
Design engineer with combined R&D and industrial experience in developing analog/mixed signal ICs for applications including inductive position sensors and imager readouts. Proven abilities with widely used blocks including (but not limited to) filter, amplifier, ADC, DAC, voltage regulators, bandgap reference, ring/LC oscillator, comparator and custom digital logic circuitry. Experience with full tape-out flow including schematic design, analog/mixed-signal simulations, floor planning, layout, system-level verification and chip measurements. Strong familiarity with industry standard tools and instruments used for design, verification and testing such as Cadence, Synopsys, Mentor Graphics, and Keysight. Frontend digital hardware design (ASIC/FPGA) experience using Verilog HDL. Considerable exposure to ASIC backend flow (synthesis and PnR) using Synopsys Design Compiler and Cadence Innovus. Skilled with programming platforms such as MATLAB, C++, C#, Perl, UNIX Shell and VB. Strong education with Ph.D. and MSc. degrees in Electronics Engineering along with several peer-reviewed articles in IEEE journals.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Perl | Python | Scilab | Software Developer | Spectre | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Filters | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB | System: Test Equipment | System: Test Programming |
Dejan Mirkovic
Electronics Engineer and Researcher with a demonstrated history of working in the higher education industry. Skilled in CAD/EDA tools for ASIC, PCB and FPGA design, scripting and programming. Education professional with a PhD in Electrical Engineering and Computer Science from University of Nis, Faculty of Electronic Engineering Nis, Serbia.
SKILLS
AREA OF EXPERTISE
Pooja bilkar
SKILLS
- C/C++ | Cadence Virtuoso | Python | Verilog |
AREA OF EXPERTISE
Ahmed Ramzy
SKILLS
- C/C++ | Octave | System Verilog | Tanner L-Edit | Verilog | VHDL | ICC | DC |
AREA OF EXPERTISE
Sajal Goyal
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Igor Danilov
SKILLS
- Cadence Encounter | Cadence Virtuoso | Python | Spectre | System Verilog | Tcl/Tk |
AREA OF EXPERTISE
Luc Wong
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Jiabin.Lv
physical design engineer.
7 years experience of backend design.
SKILLS
- Cadence Encounter | Calibre | Perl | Tcl/Tk |
AREA OF EXPERTISE
Lakshya Kailkhura
SKILLS
AREA OF EXPERTISE
Vincent Pinon
SKILLS
pranay reddy
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Verilog |
AREA OF EXPERTISE
Sandipan Sinha
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | Verilog |
AREA OF EXPERTISE
James Tandon
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Eagle CAD | Eldo | Leadership | Magic CAD | Matlab | Octave | Perl | Python | Scilab | Software Developer | System Verilog | Verilog |
AREA OF EXPERTISE
Anton Balbekov
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Leadership | Netgen | Python | SKILL | Software Developer | Spectre | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: Power Integrity |
Asier Goikoetxea
SKILLS
- C/C++ | System Verilog | Verilog |
AREA OF EXPERTISE
Laurent Lamesch
HW development engineer
AREA OF EXPERTISE
- Analog: Design | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Test Equipment |
JON MUNOA
AREA OF EXPERTISE
Yuan Mei
An experimental physicist through sensor and instrumentation development.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Leadership | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |
ABDULLAH RAZA Khan
SKILLS
- C/C++ | Synthesis | Digital design |
AREA OF EXPERTISE
ALAIN POTTECK
VLSI design project manager
SKILLS
AREA OF EXPERTISE
Antonio Agripino
Master's student at UFCG. Work with Cadence tools. I work with AMS and digital circuits (using Verilog language) and analog layout as well.
SKILLS
AREA OF EXPERTISE
Michael Welling
AREA OF EXPERTISE
Brian Glod
AREA OF EXPERTISE
- Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Mohammed Nabeel
Learner for life
SKILLS
- Perl | Python | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Mahmoud Youssuf Ahmad
Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Federico Paredes
Digital designer experienced in high-speed ASICs for optical/copper transceivers, including DSPs, error correction and SoC support.
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Python | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
Muhammad Awais Bin Altaf
SKILLS
- Cadence Virtuoso | Calibre | Matlab | Spectre | Verilog |
Caio Alonso da Costa
SKILLS
- C/C++ | Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Leonel ACUNHA GUIMARAES
SKILLS
- Cadence Virtuoso | Verilog | VHDL |
AREA OF EXPERTISE
Yao Ming Kuo
Hardware design engineer
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | Verilog |
AREA OF EXPERTISE
Alfonso Chacon-Rodriguez
Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design.
Fiction writer (National Literature Award for Novel, 2011, Costa Rica)
SKILLS
- Calibre | Eldo | Electric CAD | Matlab | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Ahmed Agiza
SKILLS
- Verilog |
AREA OF EXPERTISE
ardencaple
Semiconductor professional with 40 years experience.
I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.
AREA OF EXPERTISE
Paulo Roberto Bueno de Carvalho
Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes.
He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.
SKILLS
- C/C++ | Cadence Encounter | Python | System Verilog | Verilog | VHDL |
Hossam Hassan
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming | System: PCB |
Ernesto Conde
Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | ngspice | Python | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Hasan Mohamed
AREA OF EXPERTISE
Youstina Maher
SKILLS
- System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
HALIM
Lecturer
UiTM
SKILLS
AREA OF EXPERTISE
Mahmoud Abdelgawad
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Mostafa Elbediwy
Teaching assistant for ASIC/FPGA and digital ICs courses.
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Matlab | System Verilog | Verilog |
AREA OF EXPERTISE
fabien andrade
Graduated with a Micro-electronics Master from Bordeaux university, France, I have now 18 years of experience.
Worked in France, England, Belgium and Brazil, within 5 companies.
Implemented physical design flows, recruited, trained and supervised trainees to experienced engineers, I have a vast experience in setting up complete flow (2 companies were startups), as well as signing off important design within NXP and CSR, all to successful first time right silicons.
Able to work in total independence as well as within a team, I consider myself as optimist, result focused, with attention to detail while keeping a good trade between time to market and risk taking.
SKILLS
AREA OF EXPERTISE
Mostafa El Naggar
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | Verilog |
AREA OF EXPERTISE
Jose Maria Hinojo
SKILLS
- Allegro | Altium | C/C++ | Cadence Assura | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Perl | Tcl/Tk | VHDL |
AREA OF EXPERTISE
Tigran Poghosyan
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Hercules | Python | Tcl/Tk |
AREA OF EXPERTISE
Rakesh Singanahalli
Hello I am Rakesh , I am pursuing my Under Graduation in Electronics and Communication Engineering at KLE Technological University, Hubballi. I am looking ahead work in Digital VLSI Domain. :D
SKILLS
- C/C++ | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Siddhant Gandhi
SKILLS
AREA OF EXPERTISE
Vamshidhar Reddy
I am passionate VLSI trainee looking to explore my skills and build few projects which enhance my coding and debugging skills.
SKILLS
- C/C++ | Cadence Virtuoso | Verilog |
AREA OF EXPERTISE
Tung Hoang
R&D Engineer
SKILLS
- Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Vivek Parmar
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | ngspice | Octave | Python | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |
Artur Darbinyan
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Hercules | Leadership | SPICE Opus | Verilog |
AREA OF EXPERTISE
CHDL Custom High-Speed Digital Logic
We are group of experienced engineers working in Front-End Digital Logic Design.
AREA OF EXPERTISE
Ippei Akita
An analog mixed-signal circuit designer for low-power precision sensor interfaces. See https://staff.aist.go.jp/ippei.akita/
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Python | Spectre | Verilog |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: Chip Editing | System: PCB | System: Test Equipment |
wilfred kisku
PhD Scholar
SKILLS
- System Verilog | System-C | Verilog |
AREA OF EXPERTISE
Joseph Kiniry
Dad. Partner. Scientist. Activist. Maker. — He/His
SKILLS
- C/C++ | Cadence Virtuoso | Eagle CAD | Leadership | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | Bluespec | Chisel | EDA R&D |
AREA OF EXPERTISE
- Academic: Research | Business: Design Services | Business: Management | CAD: Tool Development | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: Quality Assurance | System: Test Programming | Miscellaneous: Formal Methods |
Stefano
SKILLS
- C/C++ | Matlab | System Verilog | Tcl/Tk |
AREA OF EXPERTISE
Pepijn de Vos
AREA OF EXPERTISE
Rahul Behl
SKILLS
- Perl | Python | System Verilog | Verilog |
AREA OF EXPERTISE
KUMAR SAKET
AREA OF EXPERTISE
Arvind Shrivastava
SKILLS
AREA OF EXPERTISE
Pratika Tripathi
I am Pratika Tripathi. I am in my final year of Btech. I am very interested in physical designing of IC. I had even taken 3 courses of kunal ghosh sir on physical design, stay, and cts.
I am doing my final year project in physical design.
AREA OF EXPERTISE
Kiran Prasad Kanaparthi
SKILLS
- C/C++ | Leadership | Perl | Python | System Verilog |
AREA OF EXPERTISE
Hanssel Morales
AREA OF EXPERTISE
RAJESH M
SKILLS
- C/C++ | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Bhuwan Kaushik
AREA OF EXPERTISE
Amit Bachiphale
SKILLS
AREA OF EXPERTISE
Chaitanya CVS
SKILLS
- Perl | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
Mandala Sai Uthej
SKILLS
- Verilog |
AREA OF EXPERTISE
Juha Häkkinen
Ph.D. in electrical engineering, 25 years experience in mixed-signal IC design
SKILLS
AREA OF EXPERTISE
ADITYA ANAND
SKILLS
- Cadence Encounter | Matlab | ngspice | Python | System Verilog | Tcl/Tk | Verilog |
Jan Bělohoubek
AREA OF EXPERTISE
sampath vp
Semiconductor
SKILLS
- Cadence Encounter | Leadership | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Mustafa Khairallah
I am a Ph.D. student at the School of Physical and Mathematical Sciences, NTU, Singapore. I co-designed the Romulus and Remus families of lightweight authenticated encryption modes with Tetsu Iwata, Kazuhiko Minematsu and Thomas Peyrin, which are the basis of three candidates for the NIST Lightweight Cryptography Competition. Previously, I got my BSc. in Electronics Engineering from Alexandria University, Egypt. My main research focus is the practical aspects of Symmetric Key Cryptography, which includes: Physical Security, Hardware Implementations, Practical Cryptanalysis and Primitive Design. Previous research projects also included the acceleration of Fully Homomorphic Encryption and Design and Verification of Digital Circuits.
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL | perl |
AREA OF EXPERTISE
Ken Pettit
Digital Systems and Software Engineer (formerly in management VP and Director of engineering).
SKILLS
- C/C++ | Leadership | Software Developer | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Loester Franco Botelho
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Alexander Stanitzki
Analog/MS/RF IC designer
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Diva | Leadership | Python | SKILL | Spectre | Verilog |
Bilal Zafar
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Leadership | Magic CAD | Matlab | ngspice | Perl | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Gaurav Kumar K
PhD Student, School of Electrical and Computer Engineering, Purdue University, USA.
Research interests include Mixed Signal Circuits, High Speed Circuits and Digital System Design
SKILLS
- C/C++ | Cadence Virtuoso | Eagle CAD | Matlab |
AREA OF EXPERTISE
Tore Leikanger
SKILLS
- C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Octave | Python | Software Developer | System Verilog |
AREA OF EXPERTISE
Boobalan Deiveegan
SKILLS
AREA OF EXPERTISE
M. Shalan
AREA OF EXPERTISE
Pavan Sai
I am a final year B.Tech undergrad from India highly passionate about digital system design.
SKILLS
- C/C++ | Leadership | Matlab | Python | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
vasundhara sanivarapu
SKILLS
AREA OF EXPERTISE
Bill Patterson
AREA OF EXPERTISE
Arya Reais-Parsi
PhD Student @ UC Berkeley, formerly SWE @ Google
SKILLS
- C/C++ | Python | Software Developer | Verilog | VHDL |
AREA OF EXPERTISE
Daniel Limbrick
I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.
SKILLS
AREA OF EXPERTISE
Sathyanarayanan
I am accomplished digital design engineer having 8 years of industrial expertise .
I am currently working on IP design and IP integrations stuffs .
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Verilog |
AREA OF EXPERTISE
Ahmed Yiwere
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | ngspice | Perl | Python | System Verilog | Verilog | VHDL |
