profiles search for area of expertise: Analog-Amplifiers
Analog full custom design experience of Low power VOltage regulators, Bandgap reference, calibration circuits and common mode receiver. worked on SERDES IP (up to 12Gbps) compliant with USB 3.1 and SATA protocols. AS ESD ENgineer for SERDES IP Improved existing ESD network simulation strategy and ESD network for robust ESD performance reliability and automated existing current density flow for ESD for better efficiency. Technology Nodes: 14nm(FINFet), 28nm(FDSOI) 28 nm,40nm,90nm,180nm (Bulk)
I am an Analog Designer passionate about building and exploring new and novel integrated circuits to create a better world.
I received the B.S. degree in Industrial Electronics Engineering from the Universitat Politècnica de Catalunya, Spain, in 2007, and the M.S. degree in Micro- and Nanoelectronics Engineering in 2009 and the Ph.D. degree in Microelectronics and Electronic Systems in 2015 both from the Universitat Autònoma de Barcelona, Spain. From 2006 to 2008, I was with Investigation Total Ware, S.A., Spain, where I was engaged in analog and mixed-signal circuit design for highly reliable wireless telecommunication systems. From 2008 to 2015, I was with the Integrated Circuits and Systems design group at the Institut de Microelectrònica de Barcelona, CNM, CSIC, Spain, designing low-power high-precision mixed-signal ASICs for integrated smart sensors and IP blocks. From 2015 to 2016, I was with Broadcom Ltd., Barcelona, Spain, developing low-power CMOS IPs like low-temperature-drift oscillators, varible-temperature-coefficient current/voltage generators, temperature sensors, cross-domain level shifting and biasing circuits, touch-sensor transmitter drivers. I am co-author of 12 publications and participant in several research and industrial projects using a wide range of CMOS technology nodes. I am recipient of the 2007 Highest Grade Point Average in the Graduating Class Award, the 2014 Best Paper Award and the 2015 Student Best Paper Award Honorable Mention. My skills include: high-performance continuous-time/switched-capacitor circuits such as low-power high-resolution ADCs/DACs using Class-AB OpAmps; system high-level modeling (SciPy/Sage, Matlab); system electrical-level modeling (Verilog/-A/-AMS); EKV circuit-level modeling; full-custom IC design cycle (gEDA Tools/Cadence Virtuoso: from schematics to layout and verification); development of low-noise and low-distortion test equipment (including microcontrollers and FPGAs) and software (using C++, Tcl, VB, Python); and, experimental IC measures and parameter extraction.
AREA OF EXPERTISE
- Analog | Analog IC | Analog IC Design | Analog-Amplifiers | Analog-Layout | Analog-Mixed Signal-DV | Analog-Modeling | Analog-Simulation | Analog-Verification | ASIC Design/Verification | Automatic Circuit Design | CAD-Dev | CAD-Scripts | Communication and Signal Processing | Design Automation | Industrial Engineering | signal processing | SOC-DV | SOC-Packaging | System-PCB | System-Power-Integrity | System-Signal-Integrity | Analog-ADC | Analog-LDO | Digital-DV | System-Filters |
Electrical Engineer M.Sc. Microelectronics
I'm an AMS Design engineer. I like the IC design world and my recent goal is to be a scientist :)
Taher Kourany joined Scenario Design Services, Cairo, Egypt as a Senior IC Design Consultant in 2016. He received B.Sc Degree in electronics and communications engineering from Ain-Shams University, Cairo, Egypt, in 2012. He received M.S. degree in electronics from the American University, Cairo, Egypt, in 2015. Until October 2015 he was a Research Assistant with the Center of Nanoelectonics and Devices Research Labs at Zewail City for Science and Technology. Mr. Kourany has published papers in the field of time complexity reduction algorithms of floorplan representations, area and wirelength minimization, Pareto-front multi-objective optimization algorithms of highly chaotic systems. His current research interests include high linearity Power Amplifiers, time complexity reduction algorithms, data structures, parameters estimation of highly chaotic systems, and the synthesis of analog IC design and layout.
Analog IC design engineer with expertise in designing analog building blocks variable gain amplifiers, active filters, frequency synthesizer (integer-N PLLs), voltage regulators.
I am an Analog/mixed signal IC designer. I worked with different technologies like ams035, xh035 and st 130nm.
I have more than five years’ experience in electronics integrated circuits industry. I have been involved in more than six silicon runs which were all successful and meeting expectations.
I have been working on Analog/Mixed-Signal Integrated Circuits design since last 16 years. I graduated from NED UET, Karachi in 2001 and then worked with Avaz Networks, a Silicon-Valley Company on RTL design and verification of a high-density Line Echo Cancellation Engine for a couple of years. Joined Linkoping University, Sweden in 2003 for Masters in SOC, which concluded with a Masters Thesis on Sigma-Delta Modulators with Fraunhofer Institute of Integrated Circuits, Germany in 2005. The same year I joined University of Trento and Fondazione Bruno Kessler, Trento, Italy for my PhD on Readout Interface Design for MEMS Capacitive Microphones. Worked with ST-Microelectronics, Milano and Analog-Devices, Copenhagen as a Guest PhD Student. This Phd results in 20+ publications and 2 patents with 3 successful MEMS Readout ASICs.
Valparaiso University - College of Engineering - ECE professor
Analog IC designer with knowledge and experience related to topics in analogl full-custom IC design such as current mirrors, single and differential amplifiers, bandgaps circuits and charge pump.