Tag results for: area of expertise

Engineering Electronic student of National University of Cordoba (UNC), Argentina. Active member of Robust Circuits and Systems Laboratory (LCSR), in exact and natural sciences faculty (FCEFyN).

SKILLS

Analog and Mixed Signal Integrated Circuit Design | Electric CAD | LTspice | Octave | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Signal Processing |

Arun kothinti

SKILLS

C/C++ | Matlab | IOT | embedded systems |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Business: Marketing |

Mahesh Bhat K

Still a Bachelor student..Trying to get know more always!!

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Vineeth Shirurmath

Student - KLE Technological University , Hubli

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Academic: Student |

Sai Srinivas TNS

SKILLS

Magic CAD | ngspice | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student |

Mustafa Sami

SKILLS

Cadence Virtuoso | Calibre | Matlab | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Communication | Circuits: Filters | Circuits: Power Management |

Krishna Ruparelia

SKILLS

Cadence Virtuoso | ngspice | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Akshay Godse

SKILLS

Cadence Virtuoso | Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Viraj Bharadwaj Korede

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Octave | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

ABHISHEK RAGHAVENDRA PAMADI

I am Abhishek Pamadi , studying engineering in KLE Technological University, I have keen interest in VLSI domain

SKILLS

Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Xianliang Chen

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Sandeep Gunturi

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Christian Lee Prather

Computer Science and Mechanical Engineering student

SKILLS

C/C++ | Eagle CAD | Matlab | Python |

AREA OF EXPERTISE

Academic: Student |

Nathan Tang

Student at Poolesville High School interested in computer science and engineering

SKILLS

C/C++ | Matlab | Python |

AREA OF EXPERTISE

Academic: Student |

Sajal Goyal

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | SoC: Verification |

Aditya Mudgal

Doing Mtech in VLSI Design from IIIT Bangalore

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

VENKATESH

i am a student

SKILLS

Cadence Encounter |

AREA OF EXPERTISE

Academic: Student |

Wilian D. Padilha

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Software Developer | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Circuits: Communication | Circuits: Power Management |

Swapnil Rawat

I am a student pursuing my masters in the field of VLSI

SKILLS

C/C++ | Cadence Virtuoso | System Verilog |

AREA OF EXPERTISE

Academic: Student |

Kenneth Jose Rojas Rodriguez

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Python | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Circuits: Communication | System: PCB |

Hemant Juneja

SKILLS

C/C++ | Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout |

Amogh Avinash

SKILLS

C/C++ | Computer Architecture | System Verilog | UVM | Verilog |

AREA OF EXPERTISE

Academic: Student |

sudipta satpati

electrical graduate student

SKILLS

ASIC |

AREA OF EXPERTISE

Academic: Student |

Aidan Goettsch

SKILLS

C/C++ | Python | Software Developer |

AREA OF EXPERTISE

Academic: Student |

Ömer Faruk Irmak

SKILLS

C/C++ | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Student |

Armagan ERGUN

SKILLS

Cadence Encounter | Cadence Virtuoso | Eagle CAD | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Sreekar

SKILLS

Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Karim Abdel Hamid

SKILLS

C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Pavan Kumar Pothula

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Sahithi Meenakshi

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Rejoy Roy Mathews

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Digital: RTL |

Nithin Angadi

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Amruthraj Koparde

SKILLS

C/C++ | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Omar Abu El-ela

Electronics and Communication student

SKILLS

C/C++ | Eagle CAD | Matlab | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design |

Samuel dos Santos Delgado

SKILLS

C/C++ | Magic CAD | Octave | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Circuits: Signal Processing | System: FPGA Programming | System: PCB |

Sandipan Sinha

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning | System: Signal Integrity |

Constantin Runge

SKILLS

C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | Software Developer | Spectre | Julia |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Simulation | Circuits: Filters | Circuits: Signal Processing | Digital: DFT | Miscellaneous: Neural Networks |

kirti khandelwal

mtech vlsi student at iiitb

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Ganesh Prasad B K

I am an electronics engineer currently working as an intern in STMicroelectronics.

SKILLS

Cadence Virtuoso | Calibre | Eldo | Matlab | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Simulation |

harshitha yadavalli

SKILLS

Cadence Virtuoso | System-C | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Simulation | Digital: RTL | SoC: ESD |

Ankit wahane

pursuing pg in vlsi system design from vnit

SKILLS

ngspice | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Shabab Alam

SKILLS

Cadence Virtuoso | Magic CAD | Matlab | Netgen | Python |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Circuits: Memory | Digital: DFT |

Martin Elaskar

Electronic engineering student. 24 years old. Currently doing a LNA design as thesis.

SKILLS

C/C++ | Matlab | Python |

AREA OF EXPERTISE

Academic: Student |

I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.

SKILLS

Magic CAD | Matlab | Netgen | ngspice | Octave | Python | System Verilog | Tcl/Tk | Verilog | VHDL | perl |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Circuits: Filters | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | System: FPGA Programming |

sai palisetti

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Sean Casey

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Gourav Saini

SKILLS

Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Rajesh Chitturi

SKILLS

System-C |

AREA OF EXPERTISE

Academic: Student |

Marwan Mohamed

I am a senior Electronics and Communications Engineering student at the Faculty of Engineering, Ain Shams University, Cairo, Egypt. I have wide knowledge and some experience in analog electronics with huge passion towards it

SKILLS

Cadence Virtuoso | Matlab | ngspice | Python |

AREA OF EXPERTISE

Academic: Student |

Yashas L.R

Technical Blogger and a Research Assistant in the field of analog VLSI Design.

SKILLS

assura | Cadence Virtuoso | Diva | Electric CAD | Magic CAD | Matlab | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Digital: RTL | System: FPGA Programming |

Jason Morris

SKILLS

Scilab |

AREA OF EXPERTISE

Academic: Student |

Mahmoud Gamal Deghadi

.

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Eldo | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student |

Alok kumar Pathak

SKILLS

Cadence Virtuoso | Magic CAD | ngspice | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design |

Hyogananda raj urs K

on my way to discover me

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Edo Dwi Christianto

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

TO_LOVEru

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

ABHIJEET SINGH JADON

currently doing mtech in vlsi domain,want to gain knowledge in physical design and asic design flow

SKILLS

System Verilog |

AREA OF EXPERTISE

Academic: Student |

Fyyaz Khan

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Christopher Brian Young

SKILLS

C/C++ | Eagle CAD | Electric CAD | Hercules | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student |

Kunal

SKILLS

Tcl/Tk |

AREA OF EXPERTISE

Academic: Student |

Mohmed Faragalla

Research Assistant and MSc student at Hamburg University of Technology (TUHH) - Microelectronics and Microsystems. Graduated from Faculty of Engineering, Ain Shams University - Electronics and Electrical Communication Section. ASIC projects I have done include: - FinFET Synchronous/Asynchronous Standard Cell Library. DOI: 10.1109/ICM.2016.7847881 - FinFET SRAM based PUF. DOI: 10.1109/ICCES.2017.8275272 - AC-DC Power Converters for Wireless Power Harvesting Unit in 350 nm CMOS Technology for Medical Implantable Devices

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design |

RISIKESH Rk

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Python |

AREA OF EXPERTISE

Academic: Student | System: FPGA Programming |

Ahmed Ghazy

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Chaitanya Parashar

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | SoC: Verification |

Venkata Nitheesh Kumar Reddy Kethu

SKILLS

C/C++ | Eagle CAD | Matlab | Octave | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Circuits: Filters | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Pradeep

Business Hotel Management

SKILLS

Cadence Encounter |

AREA OF EXPERTISE

Academic: Student |

Pooja bilkar

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Synthesis | Digital: Verification |

Khalid Ali Eissa

Fresh grad electronics engineer and a beginner circuits designer who admires analog/RF IC design. Former intern at ADI© (Egypt) and recently a junior Analog IC designer at Si-Ware Systems (Egypt). My GP was a 5G Transceiver in the band 26.5GHz - 29.5GHz, I designed the upconversion mixer (core circuit, power combiner, LO driver).