Tag results for: area of expertise

Kranthi Kumar Pamarthi

I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.

SKILLS

Magic CAD | Matlab | Netgen | ngspice | Octave | Python | System Verilog | Tcl/Tk | Verilog | VHDL | perl |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Circuits: Filters | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | System: FPGA Programming |

Armagan ERGUN

SKILLS

Cadence Encounter | Cadence Virtuoso | Eagle CAD | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Sai Srinivas TNS

SKILLS

Magic CAD | ngspice | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student |

Maria Anne San Andres

SKILLS

Matlab |

AREA OF EXPERTISE

Academic: Student |

Djamel DELLAA

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Eagle CAD | SPICE Opus | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Verification | Digital: RTL | Digital: Synthesis |

Venkata Nitheesh Kumar Reddy Kethu

SKILLS

C/C++ | Eagle CAD | Matlab | Octave | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Circuits: Filters | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Jason Morris

SKILLS

Scilab |

AREA OF EXPERTISE

Academic: Student |

Samuel dos Santos Delgado

SKILLS

C/C++ | Magic CAD | Octave | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Circuits: Signal Processing | System: FPGA Programming | System: PCB |

Rajesh Chitturi

SKILLS

System-C |

AREA OF EXPERTISE

Academic: Student |

Christian Lee Prather

Computer Science and Mechanical Engineering student

SKILLS

C/C++ | Eagle CAD | Matlab | Python |

AREA OF EXPERTISE

Academic: Student |

Hyogananda raj urs K

on my way to discover me

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Peter Atkinson

SKILLS

C/C++ | Cadence Encounter | Matlab | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Kenneth Jose Rojas Rodriguez

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Python | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Circuits: Communication | System: PCB |

Akhil Varghese Mathew

SKILLS

Cadence Virtuoso | Calibre | Matlab | Python | Spectre |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification |

Karim Abdel Hamid

SKILLS

C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

vidya baddam

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Shubham Gajbhiye

SKILLS

Electric CAD | ngspice | Verilog |

AREA OF EXPERTISE

Academic: Student |

Emre Goncu

SKILLS

Cadence Encounter | Cadence Virtuoso | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Fyyaz Khan

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Arun kothinti

SKILLS

C/C++ | Matlab | IOT | embedded systems |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Business: Marketing |

Marwan Mohamed

I am a senior Electronics and Communications Engineering student at the Faculty of Engineering, Ain Shams University, Cairo, Egypt. I have wide knowledge and some experience in analog electronics with huge passion towards it

SKILLS

Cadence Virtuoso | Matlab | ngspice | Python |

AREA OF EXPERTISE

Academic: Student |

Ömer Faruk Irmak

SKILLS

C/C++ | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Student |

Christopher Brian Young

SKILLS

C/C++ | Eagle CAD | Electric CAD | Hercules | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student |

TO_LOVEru

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Rejoy Roy Mathews

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Digital: RTL |

Muhammad Ahmed Arif

i love EL

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Edo Dwi Christianto

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Marouf H Khan

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Student |

SASWAT PADHY

SKILLS

Cadence Virtuoso | ngspice | Verilog |

AREA OF EXPERTISE

Academic: Student |

ThiagoLima

SKILLS

C/C++ | Matlab |

AREA OF EXPERTISE

Academic: Student |

Pradeep

Business Hotel Management

SKILLS

Cadence Encounter |

AREA OF EXPERTISE

Academic: Student |

Swapnil Rawat

I am a student pursuing my masters in the field of VLSI

SKILLS

C/C++ | Cadence Virtuoso | System Verilog |

AREA OF EXPERTISE

Academic: Student |

Kunchala Jaya Naga Sai Bhargav

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Student |

OPNESH DEWANGAN

PURSUING M-TECH IN VLSI SPECIALIZATION , FROM IIIT BANGALORE

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

harshitha yadavalli

SKILLS

Cadence Virtuoso | System-C | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Simulation | Digital: RTL | SoC: ESD |

sai palisetti

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Kris

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Krishna Ruparelia

SKILLS

Cadence Virtuoso | ngspice | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Ahmed Ghazy

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Chaitanya Parashar

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | SoC: Verification |

Ganesh Prasad B K

I am an electronics engineer currently working as an intern in STMicroelectronics.

SKILLS

Cadence Virtuoso | Calibre | Eldo | Matlab | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Simulation |

kirti khandelwal

mtech vlsi student at iiitb

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

sudipta satpati

electrical graduate student

SKILLS

ASIC |

AREA OF EXPERTISE

Academic: Student |

Pooja bilkar

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Synthesis | Digital: Verification |

ABHIJEET SINGH JADON

currently doing mtech in vlsi domain,want to gain knowledge in physical design and asic design flow

SKILLS

System Verilog |

AREA OF EXPERTISE

Academic: Student |

Darshan Guled

hello, my name is Darshan Guled, i am an engineering student and i am working on PICO RISc processor and RAVEN chip,

SKILLS

C/C++ | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Constantin Runge

SKILLS

C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | Software Developer | Spectre | Julia |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Simulation | Circuits: Filters | Circuits: Signal Processing | Digital: DFT | Miscellaneous: Neural Networks |

Amogh Avinash

SKILLS

C/C++ | Computer Architecture | System Verilog | UVM | Verilog |

AREA OF EXPERTISE

Academic: Student |

Sajal Goyal

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | SoC: Verification |

Aditya Mudgal

Doing Mtech in VLSI Design from IIIT Bangalore

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

sai teja reddy g

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Student |

Shubham Pandey

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Sean Casey

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Sreekar

SKILLS

Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Prasanna Kumar Talari

just a beginner in asic

SKILLS

C/C++ | Matlab | Octave | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Disha Gulur

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Student |

Shivani Shah

SKILLS

C/C++ | Matlab | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Alok kumar Pathak

SKILLS

Cadence Virtuoso | Magic CAD | ngspice | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design |

Hemant Juneja

SKILLS

C/C++ | Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout |

Pavan Kumar Pothula

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Sandipan Sinha

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning | System: Signal Integrity |

Akshay Godse

SKILLS

Cadence Virtuoso | Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Juanjo Garrido Serrato

SKILLS

VHDL | C | C++ | matlab |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Shabab Alam

SKILLS

Cadence Virtuoso | Magic CAD | Matlab | Netgen | Python |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Circuits: Memory | Digital: DFT |

Sparsh Chopra

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Student |

VENKATESH

i am a student

SKILLS

Cadence Encounter |

AREA OF EXPERTISE

Academic: Student |

Ashbir Aviat Fadila

Analog and Mixed Signals Engineering Students

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student |

Iago Sergio Pinheiro Pereira

SKILLS

C/C++ | Cadence Virtuoso | Electric CAD | Matlab | Octave | Python | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Simulation | Circuits: Signal Processing |

Xianliang Chen

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Khalid Ali Eissa

Fresh grad electronics engineer and a beginner circuits designer who admires analog/RF IC design. Former intern at ADI© (Egypt) and recently a junior Analog IC designer at Si-Ware Systems (Egypt). My GP was a 5G Transceiver in the band 26.5GHz - 29.5GHz, I designed the upconversion mixer (core circuit, power combiner, LO driver).

SKILLS

Cadence Virtuoso | Calibre | Matlab | ADS | Sonnet |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation |

Omar Abu El-ela

Electronics and Communication student

SKILLS

C/C++ | Eagle CAD | Matlab | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design |

Brandon

SKILLS

C/C++ | Leadership | Python |

AREA OF EXPERTISE

Academic: Student |

Mahmoud Gamal Deghadi

.

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Eldo | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student |

Antonio Agripino

Master's student at UFCG. Work with Cadence tools. I work with AMS and digital circuits (using Verilog language) and analog layout as well.

SKILLS

Cadence Encounter | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Digital: Placement and Routing | Digital: Synthesis |

Sheung Lu

Graduate student working on CMOS based biosensors.

SKILLS

Cadence Encounter | Cadence Virtuoso | Matlab | Python | Spectre |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Kunal

SKILLS

Tcl/Tk |

AREA OF EXPERTISE

Academic: Student |

Mustafa Sami

SKILLS

Cadence Virtuoso | Calibre | Matlab | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Communication | Circuits: Filters | Circuits: Power Management |

JBU IC Design Group 1

Students in Introduction to IC Design Course working on an Encryption design for a class project

SKILLS

Electric CAD | VHDL |

AREA OF EXPERTISE

Academic: Student |

Mohmed Faragalla

Research Assistant and MSc student at Hamburg University of Technology (TUHH) - Microelectronics and Microsystems. Graduated from Faculty of Engineering, Ain Shams University - Electronics and Electrical Communication Section. ASIC projects I have done include: - FinFET Synchronous/Asynchronous Standard Cell Library. DOI: 10.1109/ICM.2016.7847881 - FinFET SRAM based PUF. DOI: 10.1109/ICCES.2017.8275272 - AC-DC Power Converters for Wireless Power Harvesting Unit in 350 nm CMOS Technology for Medical Implantable Devices

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design |

Mahadev Shiva Bhat

I am enthusiastic student in SoC designing

SKILLS

C/C++ | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Salma Hasan

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Jacob J Bushlack

SKILLS

C/C++ | Electric CAD | Octave | VHDL |

AREA OF EXPERTISE

Academic: Student |

Francisco Gomes

SKILLS

C/C++ | Python |

AREA OF EXPERTISE

Academic: Student |

Wilian D. Padilha

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Software Developer | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Circuits: Communication | Circuits: Power Management |

Sandeep Gunturi

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Viraj Bharadwaj Korede

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Octave | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Avinash k Patil

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Academic: Student |

RISIKESH Rk

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Python |

AREA OF EXPERTISE

Academic: Student | System: FPGA Programming |

Sahithi Meenakshi

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Martin Elaskar

Electronic engineering student. 24 years old. Currently doing a LNA design as thesis.

SKILLS

C/C++ | Matlab | Python |

AREA OF EXPERTISE

Academic: Student |

Lalith Kota

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Octave | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Student |

Pranav Tippa

SKILLS

C/C++ | Leadership | Python |

AREA OF EXPERTISE

Academic: Student |

Mahesh Bhat K

Still a Bachelor student..Trying to get know more always!!

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Aidan Goettsch

SKILLS

C/C++ | Python | Software Developer |

AREA OF EXPERTISE

Academic: Student |

Vineeth Shirurmath

Student - KLE Technological University , Hubli

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Academic: Student |

Amruthraj Koparde

SKILLS

C/C++ | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Sultan Bepari

Hello I'm sultan, and I'm from KLE technological University hubli and I'm very exited to do this course on picorisc.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Nithin Angadi

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Shivam Potdar

RISC-V Enthusiast GSoC 2020 @ FOSSi Foundation RA @ CAD Lab, IISc Bengaluru, India EE Senior @ NITK Mangalore, India

SKILLS

C/C++ | Eagle CAD | Matlab | ngspice | System Verilog | Verilog | c |

AREA OF EXPERTISE

Academic: Student | CAD: Scripting | Digital: RTL | Miscellaneous: Neural Networks | SoC: ESD | System: FPGA Programming |

Gourav Saini

SKILLS

Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

ABHISHEK RAGHAVENDRA PAMADI

I am Abhishek Pamadi , studying engineering in KLE Technological University, I have keen interest in VLSI domain

SKILLS

Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Titouan Quennet

SKILLS

C/C++ | Python |

AREA OF EXPERTISE

Academic: Student |

Nikhil G P V Y

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Student |

Ankit wahane

pursuing pg in vlsi system design from vnit

SKILLS

ngspice | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Nathan Tang

Student at Poolesville High School interested in computer science and engineering

SKILLS

C/C++ | Matlab | Python |

AREA OF EXPERTISE

Academic: Student |

ganesh deshmukh

SKILLS

Eagle CAD | Python |

AREA OF EXPERTISE

Academic: Student |

Tharakram Korripadu

SKILLS

C/C++ | Perl | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Arjun Rakheja

SKILLS

Python |

AREA OF EXPERTISE

Academic: Student |

Lucas Heraldo Duarte

Engineering Electronic student of National University of Cordoba (UNC), Argentina. Active member of Robust Circuits and Systems Laboratory (LCSR), in exact and natural sciences faculty (FCEFyN).

SKILLS

Analog and Mixed Signal Integrated Circuit Design | Electric CAD | LTspice | Octave | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Signal Processing |

Karan Kumar

SKILLS

Cadence Virtuoso | Spectre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student |

Prem Kumar A

A Mixed signal designer aspirant

SKILLS

Cadence Virtuoso | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student |

Vamshidhar Reddy

I am passionate VLSI trainee looking to explore my skills and build few projects which enhance my coding and debugging skills.

SKILLS

C/C++ | Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | Digital: Synthesis |

Diego Alessandro Bravo Pacheco

SKILLS

VHDL |

AREA OF EXPERTISE

Academic: Student |

Pascal Sossou

I like Basketball

SKILLS

Python | Java | LISP |

AREA OF EXPERTISE

Academic: Student |

Chanon Khongprasongsiri

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Lucas Gonzalez-Rey

SKILLS

Leadership | Python |

AREA OF EXPERTISE

Academic: Student |

Kevin Kiningham

SKILLS

C/C++ | System Verilog |

AREA OF EXPERTISE

Academic: Student |

Pavan Kumar Kori

current I am doing postgraduation in a Micro and Nanoelectronics

SKILLS

Cadence Virtuoso | ngspice | Python |

AREA OF EXPERTISE

Academic: Student |

Hatem Elfekey

SKILLS

Circuit Design |

AREA OF EXPERTISE

Academic: Student |

P Santosh Kumar Patra

I am a final year Masters student of NIT Rourkela, I am interested in SoC designing using RISCV ISA

SKILLS

C/C++ | Matlab | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Luís Henrique Rodovalho Moreira de Lima

SKILLS

Cadence Virtuoso | ngspice | Octave |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Circuits: Signal Processing |

Vivek Parmar

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | ngspice | Octave | Python | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Modeling | Analog: Simulation | Circuits: Memory | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Test Equipment |

Risto Pejasinovic

SKILLS

C/C++ | Eagle CAD | Electric CAD | ngspice | Python | Software Developer | System Verilog | System-C | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Yaswanth Kumar Cherivirala

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | Spectre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Modeling | Circuits: Power Management |

Gustavo Linhares

i'm an eletronic engineer there are studing to became an IP desing

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Circuits: Signal Processing | System: FPGA Programming |

Nithesh Kandan

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Sancheevan Sathanantharajah

SKILLS

C/C++ | Eagle CAD |

AREA OF EXPERTISE

Academic: Student |

Yashas L.R

Technical Blogger and a Research Assistant in the field of analog VLSI Design.

SKILLS

assura | Cadence Virtuoso | Calibre | Electric CAD | Matlab | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Communication | Circuits: Filters | Circuits: Signal Processing |

vineet jain

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

steven cramp

SKILLS

C/C++ | Matlab | Verilog | VHDL | spice | orcad |

AREA OF EXPERTISE

Academic: Student |

Karthekeyan Periasamy

SKILLS

Python |

AREA OF EXPERTISE

Academic: Student |

chandan shankar M

SKILLS

C/C++ | Matlab | Python | Scilab | Verilog |

AREA OF EXPERTISE

Academic: Student |

Shivam Acharya

SKILLS

Cadence Virtuoso | Electric CAD | Tanner L-Edit |

AREA OF EXPERTISE

Academic: Student |

Shaheer Sajid

Just a person trying to build a fully featured RISC-V micro-controller and looking cool :)

SKILLS

C/C++ | Eagle CAD | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | System: FPGA Programming |

KASHISH GOYAL

SKILLS

Python | Scilab | SKILL | Software Developer |

AREA OF EXPERTISE

Academic: Student |

Keerthan Nayak

SKILLS

Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student |

Pragati Tripathi

SKILLS

asic | fpga | physical design | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL |

Sean Manuel

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Student |

Nithin Angadi

I have an enthusiastic to design a SoC.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Student |

Suvrat Mishra

SKILLS

System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student |

Tanya Sharma

SKILLS

C/C++ | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student |

Saffet BULUT

SKILLS

C/C++ | Python | System Verilog |

AREA OF EXPERTISE

Academic: Student |

Hanssel Morales

SKILLS

C/C++ | Cadence Encounter | Chisel | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification |

Anish Singhani

SKILLS

C/C++ | Chisel3 | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Dennis Restle

SKILLS

C/C++ | Python | Scilab | Software Developer | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | System: FPGA Programming | System: PCB |

Bhuwan Kaushik

SKILLS

C/C++ | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Akil M

Undergraduate Student at NIT-Trichy

SKILLS

Eagle CAD | Matlab | ngspice | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Mateusz Wygrzywalski

SKILLS

Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

H Prameeth

An engineer looking forward to making a career in digital vlsi design

SKILLS

Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Túlio Severiano

SKILLS

System Verilog |

AREA OF EXPERTISE

Academic: Student |

Mandala Sai Uthej

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: ESD | SoC: Floorplanning | System: Signal Integrity |

Charles White

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Student |

Ben R

I am a High School Student, Entry Electrical Engineer, and Computer Scientist I love to tinker with stuff and to innovate new ideas.

SKILLS

C/C++ | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Student | Circuits: Signal Processing |

teekam khandelwal

SKILLS

C/C++ | Eagle CAD | Perl | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Jan Bělohoubek

SKILLS

C/C++ | Magic CAD | ngspice | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Digital: RTL | Digital: Synthesis | Digital: Verification |

Subha Sarkar

SKILLS

Cadence Virtuoso | Calibre | Electric CAD | Verilog |

AREA OF EXPERTISE

Academic: Student |

Nelson Rodriguez

An enthusiast of the Open Source World.

SKILLS

C/C++ | Matlab | Python | Verilog | Linux |

AREA OF EXPERTISE

Academic: Student |

Edwil Fernandes

SKILLS

C/C++ | Electric CAD | Matlab | ngspice | Python | Scilab | Verilog |

AREA OF EXPERTISE

Academic: Student |

Lucas Skackauskas Gino

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Student |

Elias Vieira

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Digital: Placement and Routing | Digital: RTL |

Prabhat Khedgarkar

I have completed my M.Tech in VLSI Design from NIT Hamirpur, looking for a career in the VLSI Design.

SKILLS

C/C++ | Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Shubham Roy

SKILLS

ngspice | Octave | VHDL | fpga |

AREA OF EXPERTISE

Academic: Student |

Akhil

SKILLS

C/C++ | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student |

Michael Irsch

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Hene Stuchi Saud

SKILLS

C/C++ | Cadence Virtuoso | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

santosh lamani

i am engineering final year student and i am doing VLSI project

SKILLS

Cadence Encounter | Cadence Virtuoso | Perl |

AREA OF EXPERTISE

Academic: Student |

A F M Sajidul Qadir

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Student |

Junichiro Kadomoto

PhD student at UTokyo

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Python | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Student |

Henrique Oliveira Leite Aroeira de Assis

Electrical Engineer, pursuing a Masters in Microelectronics

SKILLS

C/C++ | Cadence Virtuoso | Leadership | Matlab | Python | System Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Álvaro Jover Álvarez

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

SREELEKSHMI R NAIR

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Loester Franco Botelho

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification | System: PCB |

Muhammad Ibrahim

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | System-C | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Academic: Student |

Abdullah Shaaban

An aspiring microelectronics student that is keen on learning state-of-the-art technology, then participating in advancing it!

SKILLS

C/C++ | Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Salam Thoithoi

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre |

AREA OF EXPERTISE

Academic: Student |

Anton Dyudin

SKILLS

Magic CAD | Python | Software Developer |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers |

Swaresh Phadke

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Rohit Kumar Singh

SKILLS

C/C++ | Software Developer |

AREA OF EXPERTISE

Academic: Student |

Afonso Roberto Plantes Neto

SKILLS

Cadence Encounter | Cadence Virtuoso | Octave | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Filters | Circuits: Signal Processing |

Ethan Polcyn

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Abbas Vahedi

SKILLS

C/C++ | Electric CAD | Matlab | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Layout | CAD: Tool Development | Circuits: Microcontrollers | Circuits: Sensors | System: FPGA Programming | System: PCB |

Kevin Dai

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Academic: Student |

John Martinuk

Graduate Teaching Assistant of Purdue University's SoCET Team

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Ataberk Olgun

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student |

Sree Sankar E

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Tore Leikanger

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Octave | Python | Software Developer | System Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Analog: Design | Analog: Layout | Digital: RTL | Digital: Synthesis | Digital: Verification | System: PCB |

Iván Rodríguez Ferrández

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Lakshmi S

Master's student in Electrical and Computer Engineering at the Georgia Institute of Technology

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Tseng BO-YU

SKILLS

C/C++ | Matlab | Octave | Python | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

Academic: Student |

Cristina Peralta Quesada

SKILLS

C/C++ | Python |

AREA OF EXPERTISE

Academic: Student |

Amir Raeesi

SKILLS

Cadence Virtuoso | Calibre | Matlab | Spectre |

AREA OF EXPERTISE

Academic: Student |

Mohammed Ashker

SKILLS

C/C++ | Cadence Virtuoso |

AREA OF EXPERTISE

Academic: Student |

Vijay Raghuwanshi

SKILLS

C/C++ | Eagle CAD | Electric CAD | Matlab | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

JENCY JACOB

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Pavan Sai

I am a final year B.Tech undergrad from India highly passionate about digital system design.

SKILLS

C/C++ | Leadership | Matlab | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | System: FPGA Programming |

Emil Martin

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Octave | Python |

AREA OF EXPERTISE

Academic: Student |

Durga G Kartha

SKILLS

Cadence Virtuoso | Matlab |

AREA OF EXPERTISE

Academic: Student |

Numan Abdullah

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eagle CAD | Magic CAD | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Miscellaneous: Neural Networks | System: Signal Integrity |

Hely Galvao Jr

Gentlemen: I have a professional background in the automotive industry, working in production management, IT and logistics where I worked as a technician, supervisor, coordinator and manager, which allowed me the following experiences: 15 years in the automotive industry, managing production and industrial logistics, planning, scheduling and production control in serial and batch production lines. With experience in dimensioning, planning and implantation of a manufacturing unit with productive start and logistics transfer without production losses. 20 years in IT management, in a soft house in the implementation, parameterization and maintenance of ERP Management projects (programming, database and systems analysis), maintenance and specification of electrical equipment, materials and systems. 4 years ago I started working with maintenance of electronics, commercial, industrial equipment , hospital, motors and transformers. Study and implementation of projects in the electrical discipline for overhead and underground networks, electrical infrastructures in residential, commercial, industrial works and maintenance of equipment in the electronics laboratory. Research and development of Brain-Machine Interfaces. As a form of relaxation and leisure, I developed an aptitude for fine arts where I have worked as a draftsman, painter, sculptor and modeler for over 20 years. I have mastery of Project Management methodology, knowledge in several SAP systems, in addition to Advanced Office package

SKILLS

C/C++ | Eagle CAD | Electric CAD | Leadership | Matlab | System-C | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Rick Yamamoto

SKILLS

C/C++ |

AREA OF EXPERTISE

Academic: Student |

Rodrigo Drummond Lima

SKILLS

C/C++ | Matlab | Octave | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Pruthvi raj Venkatesha

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Bill Patterson

SKILLS

C/C++ | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | Digital: Synthesis |

Joel Sanchez Moreno

My name is Joel Sanchez Moreno I graduated as a Computer engineer and I currently work as a full time RTL design engineer for a start up. In addition, I am doing a part-time master on High Performance Computing on the Universitat Politècnica de Catalunya (UPC)

SKILLS

Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: RTL |

Anthony Kung

Hi, I'm an Electrical & Computer Engineering + Computer Science student at Oregon State University.

SKILLS

C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | System: FPGA Programming |

Steven Herbst

I'm a PhD student working to make mixed-signal chip design more accessible, drawing inspiration from software development techniques. Prior to starting the PhD program, I spent a number of years working in industry at both the chip- and PCB-level on optical sensors and power systems.

SKILLS

C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | Spectre | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Verification | System: FPGA Programming | System: PCB |

Arya Reais-Parsi

PhD Student @ UC Berkeley, formerly SWE @ Google

SKILLS

C/C++ | Python | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Analog: Layout | CAD: Tool Development | Digital: Placement and Routing | Digital: Synthesis |

Sriharsha Ganti

Dynamic and career-oriented VLSI Verification Trainee. Looking for a responsible position as a VLSI verification engineer with a view to utilize and enhance my skills and experience towards professional and personal growth.

SKILLS

C/C++ | System Verilog | Verilog | perl | sva | c | questa sim |

AREA OF EXPERTISE

Academic: Student |

Ahmed Yiwere

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | ngspice | Perl | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Circuits: Microcontrollers | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification |

Diego Augusto Pontes

SKILLS

Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

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