profiles search for area of expertise: Academic: Research
112 results
Saravanan Nanthakumar
I am a Master Degree holder in VLSI Design. I am interested in Analog Circuit Design.
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AREA OF EXPERTISE
David Fleischer
Technology development in intergrated analog circuits.
I'm available to design analog and mixed-signal circuits as an external contractor.
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- Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Patents | Business: PCB Manufacture | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Miscellaneous: Cryptography | SoC: Verification | System: PCB |
Hesham Omran
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Eldo | Leadership | Matlab | Spectre | Tanner L-Edit | VHDL |
AREA OF EXPERTISE
Lefteris Kampianakis
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- Cadence Virtuoso | Eagle CAD | Matlab | Python | Software Developer | Spectre | VHDL | C | Java |
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Francesco Renzini
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- Cadence Virtuoso | Eagle CAD | Eldo | Matlab | Spectre | System Verilog |
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Peter Atkinson
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- C/C++ | Cadence Encounter | Matlab | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Amr Walid
Experienced Mixed Signal Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Data Conversion, Analog Circuit Design, CMOS and Mixed Signal. Strong engineering professional with a Master's degree focused in Electronics Engineering from Ain Shams University.
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AREA OF EXPERTISE
Jiabin.Lv
physical design engineer.
7 years experience of backend design.
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- Cadence Encounter | Calibre | Perl | Tcl/Tk |
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Djamel DELLAA
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- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Eagle CAD | SPICE Opus | Verilog | VHDL |
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Jorge Marin
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Santunu Sarangi
An energetic semiconductor professional with varied experience in the field of research, teaching and IC design.
📌 More than 6 years of experience in analog and mixed signal IC design.
📌 3 years of mentoring experience in analog circuit and layout design.
📌 Been part of the 4 complete IC development project.
📌 Inventor and co-inventor of 2 patents (filed) in the field of high-speed data path communication.
📌 Published few research papers with more than 30 engineering citations.
📌 6 month experience as a lead role in standard cell library development in a leading semiconductor organisation.
📌 more than 4 years of teaching experience in under-graduate electronics engineering courses.
SKILLS
- Cadence Virtuoso | Calibre | ngspice | Spectre | Tanner L-Edit | Tcl/Tk |
AREA OF EXPERTISE
Alexey Shabalovskiy
Expert in embedded and mobile applications since 2003. Has many years of experience in software and hardware development, effective team management. Excellent in the research and development, technology findings and implementations.
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- C/C++ | Leadership | Perl | Python | Software Developer | System-C |
KADAR A A
I am researcher with goals of developing high end technologies for the future.
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- C/C++ | Cadence Virtuoso | Calibre | Eldo | Leadership | Matlab | ngspice | Tanner L-Edit | Verilog | VHDL |
AREA OF EXPERTISE
Sumanta
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- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | System-C | Verilog |
AREA OF EXPERTISE
Mostafa Elbediwy
Teaching assistant for ASIC/FPGA and digital ICs courses.
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- C/C++ | Cadence Virtuoso | Calibre | Matlab | System Verilog | Verilog |
AREA OF EXPERTISE
Pascal Buchschacher
designing mixed-mode ASICs since 1986 :-)
SKILLS
- Cadence Virtuoso | Leadership | Matlab | Spectre | Verilog | VHDL |
AREA OF EXPERTISE
Hervé Pierre
Research engineer and teaching assistant in microelectronic, microsystems and bioelectronic at the university of Liège, Belgium
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- C/C++ | Electric CAD | Matlab | Python | Software Developer | SPICE Opus | VHDL |
AREA OF EXPERTISE
J. Rodriguez
Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.
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- C/C++ | System Verilog | System-C | VHDL |
AREA OF EXPERTISE
Josep Maria Sánchez Chiva
Current working in my PhD at BarcelonaTech.
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- Cadence Virtuoso | Calibre | Python | Spectre | VHDL |
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Kenji Aono
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Jon Ander Lezeta
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Sultan Bepari
Hello I'm sultan, and I'm from KLE technological University hubli and I'm very exited to do this course on picorisc.
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- C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
Arthur Lombardi Campos
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- C/C++ | Cadence Virtuoso | Calibre |
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Asfand Awan
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Mohammed Nabeel
Learner for life
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- Perl | Python | System Verilog | Verilog | VHDL |
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Eamonn Lieske
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Alessandro Paradiso
Useless Engineer
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Juanjo Garrido Serrato
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Lucas Heraldo Duarte
Engineering Electronic student of National University of Cordoba (UNC), Argentina. Active member of Robust Circuits and Systems Laboratory (LCSR), in exact and natural sciences faculty (FCEFyN).
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Arun kothinti
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- C/C++ | Matlab | IOT | embedded systems |
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Cristian Hamanaka
Analog IC Designer
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- Cadence Virtuoso | Calibre | Eldo | Python |
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Muhammad Awais Bin Altaf
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- Cadence Virtuoso | Calibre | Matlab | Spectre | Verilog |
Botond Sandor Kirei
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Aled Cuda
I'm a physics major studying at UC Berkeley interested in accelerating research and computational workloads with modern VLSI and FPGA tech.
AREA OF EXPERTISE
ِAhmed
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- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Matlab | Spectre | System Verilog | Tcl/Tk | Verilog | VHDL | vb |
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Lei Li
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Monika Sidde
Right now, I am working on physical design of ASIC.
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Valérian Lalucaa
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- Cadence Virtuoso | Matlab | Python |
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Luis Eduardo Rueda Guerrero
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- Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Scilab | System Verilog | Verilog |
Camillo
Experienced Analog Design Engineer with strong background in HV CMOS ASICs.
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Hasan Mohamed
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Wilian D. Padilha
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- C/C++ | Cadence Virtuoso | Matlab | Software Developer | VHDL |
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Ari Paasio
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- Cadence Virtuoso | Calibre | Eldo | Leadership | Matlab | Octave | Spectre |
Fernando Rangel de Sousa
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- ADS Keysight | C/C++ | EM Simulation | Octave |
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Angel Abusleme
Associate professor at Pontificia Universidad Catolica de Chile, analog and mixed-signal design
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Igor Danilov
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- Cadence Encounter | Cadence Virtuoso | Python | Spectre | System Verilog | Tcl/Tk |
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Mathieu Coustans
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- Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Spectre | System Verilog | VHDL |
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Pablo Alejandro Ferreyra
Researcher and Professor at the National University of Córdoba, Argentina.
Actual Research areas: microelectronics, embedded systems, Digital Signal Processing
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- Electric CAD | Leadership | Magic CAD |
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Muhammad Saufy Rohmad
Public University Lecturer in Computer Engineering. Passion about Computer Design.
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Mostafa El Naggar
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- C/C++ | Cadence Virtuoso | Matlab | Verilog |
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Yaswanth Raja Akaveeti
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- C/C++ |
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Jose Maria Hinojo
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- Allegro | Altium | C/C++ | Cadence Assura | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Perl | Tcl/Tk | VHDL |
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Mohammad Malik
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- Python |
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Martin Baudino
I am an Electronics Engineer with experience in IT Management, Firmware Development and Education. I spend my spare time looking for interesting projects and reading about technology trends.
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- C/C++ | Leadership | Matlab | Python | Software Developer | VHDL |
AREA OF EXPERTISE
James Tandon
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- C/C++ | Cadence Virtuoso | Calibre | Eagle CAD | Eldo | Leadership | Magic CAD | Matlab | Octave | Perl | Python | Scilab | Software Developer | System Verilog | Verilog |
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sanjay kumar singh
I am VLSI Design P.G student at N.I.T , kurukshetra
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Rejoy Roy Mathews
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- C/C++ | Cadence Encounter | Python | System Verilog | Verilog |
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Narayana Bhagirath Thota
Analog circuit designer
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Tom Darbonne
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Anton Balbekov
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- C/C++ | Cadence Virtuoso | Calibre | Leadership | Netgen | Python | SKILL | Software Developer | Spectre | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: Power Integrity |
Jose T. de Sousa
José T. de Sousa holds a PhD degree from Imperial College London (1998) and has been a university lecturer and researcher at Lisbon University (1999-present). He holds 4 international patents, is co-author of one book, and was General Chair of the Field Programmable Logic and Applications Conference in 2013. Dr. de Sousa has published more than 70 technical papers in international journals and conferences. He was co-founder and CEO of Coreworks, a semiconductor intellectual property company, which he ran from 2001 to 2013. His specialties are digital circuit design, hardware/software architecture, technical team management and semiconductor IP marketing and sales.
SKILLS
- C/C++ | Cadence Encounter | Leadership | Matlab | Octave | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |
Mahmoud Abdelgawad
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- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Syed Asad Alam
Post-doctoral research fellow in the discipline of Software and Systems, School of Computer Science and Statistics, Trinity College Dublin, with a keen interest in learning new things, specially related to computer science and engineering.
Around 4 years experience of teaching and research and more than 10 years of experience in architecture design, optimization, analysis, implementation and verification of digital and digital signal processing systems on FPGAs and ASICs. Diversifying research career by working on quantization of deep convolution neural networks. Author of three peer reviewed journal publications and five international conference publications.
AREA OF EXPERTISE
Dejan Mirkovic
Electronics Engineer and Researcher with a demonstrated history of working in the higher education industry. Skilled in CAD/EDA tools for ASIC, PCB and FPGA design, scripting and programming. Education professional with a PhD in Electrical Engineering and Computer Science from University of Nis, Faculty of Electronic Engineering Nis, Serbia.
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AGhani
Associate Professor (Electrical and Electronic Engineering)
Implantable chip design
Low power sensors
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- Cadence Encounter | Cadence Virtuoso | Leadership | Matlab | SPICE Opus | Verilog | VHDL |
AREA OF EXPERTISE
Ross Miller
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- Matlab |
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Pablo Cayuela
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- C/C++ | Electric CAD | Matlab | Octave | Scilab | Tanner L-Edit | Verilog | VHDL |
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Sunjaya
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Shabab Alam
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- Cadence Virtuoso | Magic CAD | Matlab | Netgen | Python |
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Shiwei Wang
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Kranthi Kumar Pamarthi
I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.
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Yunzhe Li
MS IC Designer, focusing on imager design in deep submicron technologies
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Apoorva J R
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Ankita Tiwari
Research Scholar
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Rohin Kumar Yeluripati
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Anthony Hastings
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- C/C++ |
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Rohit Yadav
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- C/C++ | Cadence Virtuoso | Calibre | Electric CAD | Magic CAD | Matlab | Netgen | ngspice | Octave | Python | Scilab | SKILL | Spectre | SPICE Opus | System Verilog | System-C | Tcl/Tk | Verilog |
raju sake
AREA OF EXPERTISE
Shahbaz Abbasi
Design engineer with combined R&D and industrial experience in developing analog/mixed signal ICs for applications including inductive position sensors and imager readouts. Proven abilities with widely used blocks including (but not limited to) filter, amplifier, ADC, DAC, voltage regulators, bandgap reference, ring/LC oscillator, comparator and custom digital logic circuitry. Experience with full tape-out flow including schematic design, analog/mixed-signal simulations, floor planning, layout, system-level verification and chip measurements. Strong familiarity with industry standard tools and instruments used for design, verification and testing such as Cadence, Synopsys, Mentor Graphics, and Keysight. Frontend digital hardware design (ASIC/FPGA) experience using Verilog HDL. Considerable exposure to ASIC backend flow (synthesis and PnR) using Synopsys Design Compiler and Cadence Innovus. Skilled with programming platforms such as MATLAB, C++, C#, Perl, UNIX Shell and VB. Strong education with Ph.D. and MSc. degrees in Electronics Engineering along with several peer-reviewed articles in IEEE journals.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Perl | Python | Scilab | Software Developer | Spectre | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Filters | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB | System: Test Equipment | System: Test Programming |
Saul Rodriguez
I am Assistant Professor in Bio-Electronics. My research interests include analog mixed-signal ICs for medical applications, RFIC, and ultra-low power circuits.
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- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Verilog |
AREA OF EXPERTISE
Alcides Silveira Costa
AREA OF EXPERTISE
Marco António da Mota Carvalho Silva Pereira
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Spectre | Verilog |
AREA OF EXPERTISE
Taimur Rabuske
I am a senior researcher in INESC-ID, Lisbon.
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- Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Octave | Python | Software Developer | Spectre |
AREA OF EXPERTISE
Mohmed Faragalla
Research Assistant and MSc student at Hamburg University of Technology (TUHH) - Microelectronics and Microsystems. Graduated from Faculty of Engineering, Ain Shams University - Electronics and Electrical Communication Section.
ASIC projects I have done include:
- FinFET Synchronous/Asynchronous Standard Cell Library. DOI: 10.1109/ICM.2016.7847881
- FinFET SRAM based PUF. DOI: 10.1109/ICCES.2017.8275272
- AC-DC Power Converters for Wireless Power Harvesting Unit in 350 nm CMOS Technology for Medical Implantable Devices
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Ahmad Qassem Dawoud
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- Cadence Virtuoso | Calibre | Matlab | Perl | Spectre |
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Nimit Jain
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- Cadence Virtuoso | Matlab | Spectre |
AREA OF EXPERTISE
Jhalak Sharma
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- Cadence Virtuoso | Matlab | Python | Verilog |
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Rafael Lima
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- C/C++ | Matlab | Python | Software Developer |
AREA OF EXPERTISE
Hossam Hassan
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- C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming | System: PCB |
Venkata Nitheesh Kumar Reddy Kethu
AREA OF EXPERTISE
Semiu A. Olowogemo
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Angel Diéguez
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- Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Leadership | Verilog |
AREA OF EXPERTISE
Sheung Lu
Graduate student working on CMOS based biosensors.
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- Cadence Encounter | Cadence Virtuoso | Matlab | Python | Spectre |
AREA OF EXPERTISE
Paul Liljenberg
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- C/C++ |
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Ben Marshall
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- C/C++ | Python | System Verilog | Verilog |
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Mohamed Gamal Shouman
Working as a instruments engineer, and currently working on my masters of Microelectronic Systems Design.
Passionate about designing analog/mixed signal IC's and systems
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Saroja V.S.
I am A professor
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HUGO DANIEL HERNANDEZ
Hugo Hernández received his B.S. degree in Electronic Engineering from The Industrial University of Santander, Colombia in 2005 and M.S. degree in Electrical Engineering from Polytechnic School of the University of São Paulo (EPUSP), Brazil in 2008. Hugo obtained his Ph.D degree in Electrical Engineering from University of São Paulo in 2015. He was Mixed Signal IC designer at LSITEC and DFCHIP (Brazil) where worked for 8 years, and Pos-doc of the Universidad de Sao Paulo in collaboration with ALICE-CERN as analog IC designer in the SAMPA ASIC project. He was Adjunct Professor of the Control and Automation course at the Engineering Institute (CUVG) of UFMT for 2 years. He is currently Adjunct Professor of the Department of Electrical Engineering of the Federal University of Minas Gerais (UFMG).
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- Cadence Virtuoso | Calibre | Eagle CAD | Eldo |
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Chanaka Ashan Ganewattha
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Alex Sheldon
Electrical Engineering PhD Student focusing on low noise analog and RF circuits
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Mahmoud Youssuf Ahmad
Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.
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- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Tcl/Tk | Verilog | VHDL |
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Niels Moseley
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- C/C++ | Cadence Encounter | DSP | Matlab | Python | Software Developer | Verilog | VHDL |
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Baris Volkan Yildirim
Design engineer
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- Analog CMOS Circuit | Analog IC Design | Eldo | Matlab | Python | System Verilog |
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Tan Kong Yew
My current work is as an analog mixed signal circuit designer for a government R&D institute, I am also involved in characterization and testing after the chip returns from foundry.
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Rod
I'm an engineer with experience in analog IC design both in private companies as well as academia. Experienced in design of delay locked loop(DLL), clock recovery, field detectors, voltage limiters, operational amplifiers, current mirrors, bandgap reference and so on.
Sergei Ryzhov
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Yuan Mei
An experimental physicist through sensor and instrumentation development.
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- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Leadership | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Shwetha
Analog Circuit and Layout Engineer
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Petteri Mäki
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- Verilog |
