Development of analog IP taylored to the customer's needs

• Power management
• Clock management
• References
• Data converters
• Sensors
• Front-ends
• Memories

Porting of existing analog IP from foundry/node towards the technology process desired by the customer.

• Power management
• Oscillators
• References
• Data converters
• Sensors
• Front-ends
• Memories

Modification of existing analog IP to reach specifications requested from customer.

• Power management
• Oscillators
• References
• Data converters
• Sensors
• Front-ends
• Memories

Implementation of custom analog/mixed signal layout of third party's IP.

• High current handling
• High voltage experience
• Experience in DMOS devices
• Mixed signal designs
• Ultra low power techniques
• Experience with RF frequencies
• High accuracy techniques

Design of custom ASIC for innovative products

• Power management
• Oscillators
• References
• Data converters
• Sensors
• Memories
• Verilog/VHDL
• SystemVerilog/UVM
• Cadence flow
• Synopsys flow

Implementation of digital back-end.

• Cadence flow
• Synopsys flow

Development of custom RTL designs.

• Verilog
• VHDL
• Cadence and Synopsys design flow

Verification of existing RTL against reference model or standard using UVM.

• UVM
• SystemVerilog

This design service provides physical implementation and fabrication services for developing an SoC based on the Raptor Arm Cortex M0 design...

• SoC design template based on Arm Cortex M0
• Mixed signal MCU controller including analog peripherals
• Full turn-key design service
• X-FAB 180nm technology node (XH018)

This design service provides fabrication services for developing an SoC based on the Raptor Arm Cortex M0 design template.

• SoC design template based on Arm Cortex M0
• Mixed signal MCU controller including analog peripherals
• Full turn-key design service
• X-FAB 180nm technology node (XH018)

A full turn-key design service providing die samples for an SoC based on the Raptor Arm Cortex M0 design template.

• SoC design template based on Arm Cortex M0
• Mixed signal MCU controller including analog peripherals
• Full turn-key design service
• X-FAB 180nm technology node (XH018)

ASIC Digital Design Services – Microarchitecture & RTL Design for ASIC and FPGA

• Architecture Definition
• RTL development
• IP/Block  development
• Performance tradeoff
• Evaluation, customization and IP integration
• Design Synthesis
• Timing and equivalence checking
• Post Silicon debug

System & Board Design Services including Board Design, PCB Layout, Automated Testing, Characterization & Bench Automation

• Bench Characterization and Testing
• Board Design / System Design
• Lab Automation
• Automated Testing
• System Design
• SoC Evaluation
• PCB Layout Design

Silicon & IP Validation Services include test chip development, characterization and validation

• Testchip development
• Reference Boards & Test boards development
• Layout
• IPC Certified Layout engineers
• Prototyping solutions
• Bench characterization and testing
• Jitter profile for IPs
• LDOs, BGRs, PORs and temperature sensors

HVL based ASIC/SoC Verification using SystemVerilog for module, block and system level verification.

• Module, Block & full Chip Verification
• SoC (C/SV/ASM based), Subsystem & Block/IP level verification
• Verification IP development
• Protocol expertise
• PCIe, DDRx, Ethernet, USB, eDP/DP, HDMI and ARM bus (AXI, AHB, APB)
• Testbench development
• Methodologies
• UVM, OVM and eRM
• Language expertise
• Coverage driven & Assertion based verification

Analog & Mixed Signal Layout services for complex SoCs

• Largest pool of Layout Engineers
• Ability to quickly ramp teams for new processes and methodology
• Established Training Methodology
• Ability to uncover circuit issues in the early phase of layout
• Complete Ownership of the project
• From start to hand-off

Mixed Signal Clocking System Services for PLL, Clocks, DLL, Oscillator and SerDes

• PLL
• CDR
• DLL
• Oscillator
• Ser-Des

Mixed Signal Data Convertor Services for DAC/ADCs

• Complete ADC/DAC implementations from architecture evaluation, design, verification to silicon validation
• Extensive porting and design experience (from scratch) of foundation IPs like Comparator, MUX.
• Multiple Turnkey projects on Data-Converter modules from Spec to GDSII
• High Voltage, High Precision & Low Power implementations capability

Services for DC-DC, LDO, Charge Pump, Power Circuits and Reference Generators

• Extensive design experience (from scratch) & porting of foundation IPs like BGRs, LDOs, PORs
• Complete DCDC implementations from architecture evaluation, design /verification to silicon validation
• Turnkey projects on PM modules from Spec to GDS
• High Voltage & High Current experience.
• Ultra/Low Power implementations

Mixed Signal Modeling Services include marco models, analog and mixed signal and logic modeling.

• Macro Modeling
• Analog & Mixed Signal Modeling
• WREAL Modeling
• Logic Modeling
• Functional Modeling
• Performance Modeling
• Plug and Play Capability in the Test bench
• Capturing I/O impedance
• Model characterization
• Modeling tool and automation

Memory platform expertise including experience in a comprehensive set of memory compilers

• Experience of 200+ memory projects in variety of technologies
• Team involved in design, porting & characterization
• Ability to create memory at instance(FCI) or compiler level from Spec to GDSII
• Memory Complier with strong domain knowledge
• In-house tools (MC2 and Touchstone)

Technology Foundation Services include PDK development, verification and Rule Deck Development

• 180nm - 28nm CMOS
• 20nm & FinFet
• RFCMOS
• BiCMOS
• High Voltage Analog
• FDSOI
• Global Foundries
• TSMC
• X-Fab
• UMC
• Toshiba

Portfolio of services for high-speed, high-density and low-power standard cell libraries

• Faster time-for-convergence during synthesis, placement, CTS & routing
• Better ease-of-use with efficient and quicker ASIC implementation through superior routeability & area optimization

Experience in the full ASIC design flow specialising in communication protocols, memory interfaces, complex state machines and calibrators. We...

• Memory Controllers
• Memory Compiler Development
• Communication Protocols - high speed interfaces
• Cryptographic algorithms Motor Controllers and transceivers
• Codec, Digital filters
• Computer On Board Satellite
• SOC, Mixed Signal Design, Integration of IP from all leading providers
• DFT, Mbist

Experience in different nodes and technology flavours: From 10nm to 1um - more than Moore's - CMOS, BiCMOS, High Voltage and SOI.

• Fullchip/block level layout until tape-out
• Deep understanding of layout effects including – Parasitic, Antenna effects, dummy fill, isolation issues, shielding, shallow trench isolation, signal integrity, matching, parasitic performance and design for manufacturability
• Capability to generate IP views (LEF, GDS, LIB)

We have experience in wide spectrum of AMS IPs expertise. We provide either turnkey model or consultation on site support from schematic entry...

• Knowledge of high voltage technology up to 650 V
• Knowledge of High Speed, Low Power CMOS Design Techniques (22nm/40nm/65nm/90nm/130nm/180nm)
• Deep understanding in developing state-of-the-art analog IPs
• Data Converters (ADC, DAC)
• Power converters (AC-to-DC, DC-to-DC converter)
• High speed transceivers

SoC Level Implementation from RTL to GDSII, Full Hierarchical Design. Full Flat Design, Mixed Signal Design

• Mixed Signal – Analog-on-top implementation
• Mixed Signal – Digital-on-top implementation
• Low Power physical implementation Flow
• UPF/ CPF Based Implementation & verification Flow
• Multi-Power Islands, Multi-Voltage Islands design
• Multi-Mode Multi Corner Clock Tree expansion & timing closure implementation

We are expert in Cadence-based PDK development and SVRF-based Physical Verification DRC, LVS, Extraction (xRC) rule-writing and development.

• Incremental TechFile Database (ITDB) support
• Technology file for Cadence and Synopsys PnR tools
• PCELLs , CDF and Callback creation and QA
• DRC and LVS rules decks write-up and QA
• XRC and QRC extraction flow support and QA
• Fill script support
• Inductor library creation and EM simulations (inductor finder tool)

We have expertise in house that can do small to medium custom standard cell and IOs development that covers NLDM/CCS/ECSM Characterization.

• Library layout view OA, GDS, LEF & FRAM creation
• XRC/QRC netlist extraction c. I/O and Std Cells NLDM/CCS/ECSM Characterization
• Liberty Timing File (LIB) and dB generation
• CeltIC noise library cdB generation
• Verilog & VHDL view generation
• Datasheet generation
• Library validation
• Library QA in Cadence and Synopsys tools