Summary

PICORV32
community
Clifford Wolf
soft_ip
N/A
Community
N/A

Licensing

$0
$0

Maturity

Layout

Library Package

1.0
Jun 23, 2017

Certifications

icon Community Certified

Description

PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details. PicoRV32 is free and open hardware licensed under the ISC license (a license that is similar in terms to the MIT license or the 2-clause BSD license).

Features

  • Small (750-2000 LUTs in 7-Series Xilinx Architecture)
  • High fmax (250-450 MHz on 7-Series Xilinx FPGAs)
  • Selectable native memory interface or AXI4-Lite master
  • Optional IRQ support (using a simple custom ISA)
  • Optional Co-Processor Interface

Pins

NAME DESCRIPTION TYPE DIRECTION VMIN VMAX
clk clock input signal input -0.5 VDD + 0.3
resetn master reset (sense inverted) signal input -0.5 VDD + 0.3
trap error trap flag signal output -0.5 VDD + 0.3
mem_valid memory valid signal output -0.5 VDD + 0.3
mem_instr memory instruction signal output -0.5 VDD + 0.3
mem_ready memory ready signal input -0.5 VDD + 0.3
mem_addr<31:0> Memory address bus (32 bits) digital output -0.5 VDD + 0.3
mem_wdata<31:0> Memory write data (32 bits) digital output -0.5 VDD + 0.3
mem_wstrb<3:0> Memory write strobe (4 bits) digital output -0.5 VDD + 0.3
mem_rdata<31:0> Memory read data (32 bits) digital input -0.5 VDD + 0.3
vdd! Positive digital power supply power inout 3.0 3.6
gnd! Digital Ground ground inout 0 0

Parameters

Global Conditions

NAME MINIMUM TYPICAL MAXIMUM UNITS
VDD 3.3 V
Ground 0 V