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The SYMLVDS33_A1 is a 630Mbps LVDS Transceiver that operates from supply voltage

of 1.2V and 3.3V. The IP uses the Altis ATS-130-RF, 130nm CMOS technology and is compatible with the ATS-130-LP process.

Both the LVDS transmitter and receiver can be powered down by asserting the PD pins high. The receiver has an optional internal on-chip termination and no internal clock or CDR allowing a very small and compact form factor to be achieved. Fail-safe circuitry is included in the receiver to cope with open circuit conditions when the driver is in a high impedance state or the cable is disconnected from the receiver. No external compensation is needed.

The LVDS transceiver is compliant with TIA/EIA-644A standard for point-to-point configuration as well as multi-drop configuration (up to 32 parallel connected receivers).

  • Available in Altis ATS-130-RF and ATS-130-LP, 130nm CMOS technology
  • Supply Voltage Range: 3.3V ± 10%
  • Data rate of up to 630Mbps
  • Conforms to the TIA/EIA-644-A LVDS standard
  • Supports power down mode
  • With and without internal/on-chip termination (receiver) options available
  • Internal reference block
  • No. of channels: 1
  • ESD requirements are HBM 2kV, CDM 500V as per Altis I/O library capability
  • IP area of receiver is 761.6um X 138.5um
  • IP area of transmitter is 841.6um X 138.5um

Summary

Catalog ID

SY-SYMLVDS33_A1

IP Provider

design house

Designer

Symmid

Type

Hard IP

Node

130nm

Vendor

Symmid

Foundry

Altis

Process
Category

LVDS

Certifications

icon

Licensing

Info

Contact Designer

Maturity

Stage

silicon_proven

# of Tries

0

Library Package

Version

1.0

Version Date

Nov 01, 2018