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Digital level shifter between a 1.8V domain and a 3.3V domain. Matches the row height of digital standard cell set D_CELLS_3V.

  • Matches the footprint of digital standard cell set D_CELLS_3V.

Pins

Name Description Type Direction Vmin Vmax
A Low-voltage input signal input -0.5 VDD1V8 + 0.3
Q High-voltage output signal output -0.5 VDD3V3 + 0.3
VDD3V3 High-voltage supply power inout +3.0 +3.6
VDD1V8 Low-voltage supply power inout +1.5 +2.1
VSSA Common ground ground inout

Global Conditions

Name Typical Minimum Maximum Units
VDD3V3 3.3 V
VDD1V8 1.8 V
Ground 0 V
RLoad 100
CLoad 1 pF
Temp 27 -40 85 °C
Sigma 3
Corner tm ws wp

Electrical Parameters

Parameter Pin Typical Minimum Maximum Units Conditions
VOL 1.921e-08 4.144e-09 7.296e-08 V Conditions
VOH 3.3 3.3 3.3 V Conditions
TPD rise @ 3σ 1.761 1.396 2.033 ns Conditions
TPD rise @ 6σ 1.908 1.355 2.747 ns Conditions
TPD fall @ 3σ 1.968 1.609 2.389 ns Conditions
TPD fall @ 6σ 1.997 1.426 2.713 ns Conditions
IDD (leakage) 49.19 21.6 196.7 pA Conditions

Physical Parameters

Parameter Typical Minimum Maximum Units
device_area 113 µm²
area 56.56 µm²
width 9.82 µm
height 5.76 µm
LVS_errors 0
DRC_errors 0

Figure(s)

LS_3VX2_symbol.svg

Figure 1

Performance Characteristics

TPDxVDD3V3.png

Plot 1: Propagation delay vs. supply voltage VDD3V3

Summary

Catalog ID

LS_3VX2

IP Provider

community

Designer

efabless engineering

Type

Hard IP

Node

180nm

Vendor

efabless

Foundry

X-FAB

Process

EFXH018A

Category

N/A

Certifications

N/A

Licensing

Per-use

N/A

Royalty

N/A

Maturity

Stage

layout

# of Tries

78

Library Package

Version

8.0

Version Date

May 21, 2018