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SK-SGIO-IO-T040G

Sankalp

SGIO IO T040G Library is a General Purpose IO Library (GPIO) developed in 40nm TSMC G process (equivalent to TSMC 45nm General Purpose Superb). It contains LVCMOS, LVDS, Crystal Oscillator, Analog and Power Pads along with a Power Detect cell.

The cells are implemented with TSMC G process (single poly with 9 metals). It uses SVT/HVT thin-oxide 1.0 V and 1.8 V transistors. The use of deep N-well, ESD implant and LVT transistors are not required. It operates on a core supply of 0.9 / 1.0 V and I/O supply of either 1.8 / 2.5 V or 2.5 / 3.3 V with variations as specified by JEDEC. All cells are power supply sequence independent.

  • JEDEC and ONFI 2.1 compatible
  • IEEE Electrical Specification compliant
  • 40nm Single Poly TSMC G Process
  • Minimum mask cost
  • No Deep NW, ESD implant or LVT devices required
  • Core Supply of either 0.9 V or 1.0 V ±10%
  • I/O Supply of either 1.8 / 2.5 V ±10% or 2.5 / 3.3 V ±10% for LVCMOS and 1.8 V ±10% for LVDS
  • One I/O supply power/ground pair per 2 TX
  • Power supply sequence independent
  • Operating junction temperature range: −40oC to 125oC
  • ESD hardness of 2kV HBM and 500V CDM
  • Latchup immune upto ±100mA current injection
  • Low power consumption
  • Operating frequency of 200 MHz for LVCMOS and 675 MHz for LVDS
  • Over Voltage Tolerant Cells available
  • Analog Test Bus available
  • Programmable Current and Impedance Drives available
  • Supports 602 and 702 metal stacks
  • Wire-bond and Flip-chip compatible
  • Both Linear and Staggered Pad layout possible
  • Smaller Form Factor - Circuit Under Pad (CUP)

Summary

Catalog ID

SK-SGIO-IO-T040G

IP Provider

design house

Designer

Sankalp

Type

Hard IP

Node

40nm

Vendor

Sankalp

Foundry

TSMC

Process

T040G

Category

General Purpose I/O

Certifications

icon

Licensing

Info

Contact Designer

Maturity

Stage

product

# of Tries

0

Library Package

Version

1.0

Version Date

Oct 01, 2018