Summary

HYDRA_SPI_CONTROLLER
community
efabless engineering
Hard IP
350nm
efabless
X-FAB
EFXH035B
misc

Licensing

$0
$0

Maturity

prototype
11

Library Package

1
Jun 23, 2017

Certifications

icon eFabless Certified

Description

Hydra version 2.0 SPI controller digital block.

Features

  • Standard SPI slave controller
  • Dedicated register set for Hydra v2p0

Pins

NAME DESCRIPTION TYPE DIRECTION VMIN VMAX
SCK SPI clock input signal input -0.5 VDD + 0.3
RST SPI master reset signal input -0.5 VDD + 0.3
CSB SPI chip select (sense inverted) signal input -0.5 VDD + 0.3
SDI SPI data input signal input -0.5 VDD + 0.3
SDO SPI data output (tristate) signal output -0.5 VDD + 0.3
sdoena SPI data output enable (sense negative) signal output -0.5 VDD + 0.3
adcvalue<9:0> Input from ADC (10 bits) digital input -0.5 VDD + 0.3
adcdone Completion signal from ADC signal input -0.5 VDD + 0.3
bgap1ena Enable to bgap1 signal output -0.5 VDD + 0.3
bgap1trim<3:0> Trim to bgap1 digital output -0.5 VDD + 0.3
bgap2ena Enable to bgap2 signal output -0.5 VDD + 0.3
bgap2trim<3:0> Trim to bgap2 digital output -0.5 VDD + 0.3
bgap3ena Enable to bgap3 signal output -0.5 VDD + 0.3
bgap3trim<3:0> Trim to bgap3 digital output -0.5 VDD + 0.3
bgap4ena Enable to bgap4 signal output -0.5 VDD + 0.3
bgap4trim<3:0> Trim to bgap4 digital output -0.5 VDD + 0.3
bgena Enable to X-Fab bandgap IP signal output -0.5 VDD + 0.3
xtalena Enable to X-Fab xtal oscillator IP signal output -0.5 VDD + 0.3
adcena (unused) signal output -0.5 VDD + 0.3
adcrstb Enable to X-Fab ADC IP signal output -0.5 VDD + 0.3
adcconvert Conversion start to X-Fab ADC IP signal output -0.5 VDD + 0.3
VDD Positive digital power supply power inout 3.0 3.6
GND Digital Ground ground inout 0 0

Parameters

Global Conditions

NAME MINIMUM TYPICAL MAXIMUM UNITS
VDD 3.3 V
Ground 0 V

Physical Parameters

PARAMETER MINIMUM TYPICAL MAXIMUM UNITS
device_area 73276.71 µm²
area 73276.71 µm²
width 290.55 µm
height 252.2 µm
DRC_errors
LVS_errors