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Hydra v2p0 36-pin padframe

  • In-frame Crystal oscillator
  • 32 pin
  • Dedicated SPI pins

Pins

Name Description Type Direction Vmin Vmax
padSCK SPI clock input signal input -0.5 xDVDD + 0.3
xSCK SPI clock to core signal output -0.5 xDVDD + 0.3
padCS SPI chip select (sense inverted) signal input -0.5 xDVDD + 0.3
xSSN SPI chip select to core (sense inverted) signal output -0.5 xDVDD + 0.3
padSDI SPI data input signal input -0.5 xDVDD + 0.3
xSDI SPI data input to core signal output -0.5 xDVDD + 0.3
xSDO SPO data output from core signal input -0.5 xDVDD + 0.3
padSDO SPI data output (tristate) signal output -0.5 xDVDD + 0.3
en_sdo SDO output enable signal input -0.5 xDVDD + 0.3
padXI Crystal oscillator input signal input -0.5 xDVDD + 0.3
padXO Crystal oscillator output signal output -0.5 xDVDD + 0.3
xXTAL_EN Crystal oscillator enable signal input -0.5 xDVDD + 0.3
xCLKXTAL Crystal oscillator clock output signal output -0.5 xDVDD + 0.3
xA17 General purpose analog I/O signal inout -0.5 xAVDD_N + 0.3
xA16 General purpose analog I/O signal inout -0.5 xAVDD_N + 0.3
xA15 General purpose analog I/O signal inout -0.5 xAVDD_N + 0.3
xA14 General purpose analog I/O signal inout -0.5 xAVDD_N + 0.3
xA13 General purpose analog I/O signal inout -0.5 xAVDD_N + 0.3
xA12 General purpose analog I/O signal inout -0.5 xAVDD_N + 0.3
xA11 General purpose analog I/O signal inout -0.5 xAVDD_E + 0.3
xA10 General purpose analog I/O signal inout -0.5 xAVDD_E + 0.3
xA09 General purpose analog I/O signal inout -0.5 xAVDD_E + 0.3
xA08 General purpose analog I/O signal inout -0.5 xAVDD_E + 0.3
xA07 General purpose analog I/O signal inout -0.5 xAVDD_E + 0.3
xA06 General purpose analog I/O signal inout -0.5 xAVDD_E + 0.3
xA05 General purpose analog I/O signal inout -0.5 xAVDD_S + 0.3
xA04 General purpose analog I/O signal inout -0.5 xAVDD_S + 0.3
xA03 General purpose analog I/O signal inout -0.5 xAVDD_S + 0.3
xA02 General purpose analog I/O signal inout -0.5 xAVDD_S + 0.3
xA01 General purpose analog I/O signal inout -0.5 xAVDD_S + 0.3
xA00 General purpose analog I/O signal inout -0.5 xAVDD_S + 0.3
xAVDD_N Analog supply signal inout 3.0 3.6
xAVDD_S Analog supply signal inout 3.0 3.6
xAVDD_E Analog supply signal inout 3.0 3.6
xAGND_N Analog ground signal inout 0 0
xAGND_S Analog ground signal inout 0 0
xAGND_E Analog ground signal inout 0 0
xDVDD Positive digital power supply power inout 3.0 3.6
xDGND Digital Ground ground inout 0 0

Global Conditions

Name Typical Minimum Maximum Units
VDD 3.3 V
Ground 0 V

Physical Parameters

Parameter Typical Minimum Maximum Units
device_area µm²
area 3121080.5 µm²
width 1744.4 µm
height 1789.2 µm
DRC_errors 0
LVS_errors 0

Figure(s)

hydra_padframe_symbol.svg

Figure 1

Summary

Catalog ID

HYDRA_PADFRAME

IP Provider

community

Designer

efabless engineering

Type

Hard IP

Node

350nm

Vendor

efabless

Foundry

X-FAB

Process

EFXH035B

Category

N/A

Certifications

icon

Licensing

Info

Contact Designer

Maturity

Stage

layout

# of Tries

16

Library Package

Version

2.0

Version Date

Apr 27, 2018